VLSI Trained Fresher

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Kulbhushan Singh

*********@*****.***

***, *** **** *****,

Saharanpur-247001

Mob.: +91-959*******

Carrier Objective

To work in an Organization where Culture of Freedom and Working for

Initiatives is Ensured, Facilitating my Contribution through Thoughts and

Action to the Company's vision and thus Achieve self-development by Playing

a Significant role in Building the Organization.

Fields of Interest

Software Development & Testing in the IT sector. Analog and Mixed Signal

VLSI Design, High speed and Low power circuit Design Techniques in

Semiconductors.

Main Subjects Studied

Analog and Digital VLSI Design, Algorithms for VLSI, CAD for VLSI, Physics

of Semiconductor Devices, IC Fabrication Technology, RF Microelectronics,

Testability and testing, MEMS and IC integration, Hardware Description

Languages.

Educational Qualifications

Master of Technology (Micro Electronics and VLSI)

Shobhit University, Meerut, India

Marks: 7.35 CGPA

Year of passing: July 2014

Year of passing: September 2014

Bachelor of Technology (Electronics and

Telecommunication)

Uttar Pradesh Technical University, Lucknow, India

Marks: 58.14%

Year of passing: July 2011

12th (Physics, Chemistry, Mathematics, Biology, English)

G.H.S.S Telam, Arunachal Pradesh

Board: C.B.S.E

Marks: 64%

Year of passing: May 2006

10th (Hindi, English, Mathematics, Science, Social

Science)

G.H.S.S Telam, Arunachal Pradesh

Board: C.B.S.E

Marks: 74%

Year of passing: May 2004

Experience

8 months intern experience at Tevatron technologies NOIDA in VLSI Frontend

design and verification.

Professional Training

1. 8 months Intern experience on front-end design (VLSI) and Verification

in TEVATRON TECHNOLOGIES NOIDA.

2. Completed 5 weeks summer training (VLSI) at DKOP Labs NOIDA.

3. Successfully completed 4 weeks Non-BSNL course at ALTTC Ghaziabad.

4. Certification in "Verilog & ORCAD".

Technical Skills

. Icarus Verilog:

Design and Verification in Verilog

. Mentor Graphics:

Modelsim SE 6.4 and 5.7

. Xilinx:

Project Navigator 13.3

. Tanner EDA

. Cadence NCSIM

Verification in System-Verilog Environment

. Hardware Description Languages: VHDL, Verilog

. Hardware Verification Languages: System-Verilog(SV)

. Back-End(VLSI): Floor-planning, Placement, Routing, Layout

. FPGA

. Basic knowledge of scripting in Shell, Perl

. OOP Concepts

. C/C++: Intermediate level of understanding

. Networking

. OS: Windows, LINUX

Projects Completed

Design KOP Pvt. Ltd.

Project Title: 10 GB Ethernet card module

Project Description:

. This 10 GB ETHERNET CARD module is used for taking the particular

data for specific computer.

. This whole module contains a parity checker and a finite state

machine(FSM)

. FSM is basically used for checking blocks of data, padding & also

the number of data bits.

. FSM is also used for switching over the job to sub modules of card

LIGHT DEPENDENT RESISTOR (LDR)

Project Title: To study the working of LDR.

Project Description:

. It is basically used to automatic switch on and switch off the

electronic circuits.

. It contains a light dependent resistance whose resistance increases

and decreases with the intensity of light.

. It is used for automatic switching of road lights.

VOTING MACHINE USING GSM COMMUNICATION

Project Description:

. It is used for the voting system by any gsm mobile phone, by

dialing a fixed gsm mobile phone number which is attached with the

voting machine.

. Works on 8 bit microcontroller.

. Store voting results and display the results.

PRIORITY ARBITER FOR SHARED MEMORY (M.TECH MINI PROJECT)

Project Description:

Design a shared memory arbiter in VHDL that allows for more than one system

to use a single shared memory module in a controlled manner. The arbiter

uses fixed priority scheme.

M.TECH THESIS

. Design and formal verification of CONTROLLER AREA NETWORK(CAN)

. It is a multi-master serial communication protocol

. The RTL based design is implemented using Verilog HDL

. Tools used: Modelsim SE 6.4, Cadence NCSIM

Seminars Presented

1. 3-D Chips and there Design Technology.

2. Asynchronous Chips and there advantages.

Research Paper Published

Controller area networks (CAN) evolution, response time analysis and

applications.

Extra Curricular Activities

I have been an active participant in cultural programs and other technical

fests at school and college level.

Personal Details

Father's name : Sumer Pal Singh

Date of Birth : 09th Aug 1989

Sex : Male

Marital status : Single

Nationality : Indian

Permanent Address : 316

New Avas Vikas

Saharanpur (247001), Uttar

Pradesh, India

Phone : +91-959*******

Strengths

I am a dedicated and result oriented professional. I am an effective

communicator with excellent interpersonal, analytical, problem solving and

organizational abilities.

Declaration

I hereby state that all the above information's and details given by me are

true to the best of my knowledge and abilities.

(Kulbhushan Singh)

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