| Resume alert | Resumes 1 - 10 of 16 |
Software Development Embedded
Freehold, NJ
... Tony Triolo: 732-***-**** Director (Immediate Supervisor) – Applied Communication Sciences Jim Hodge: 732-***-**** Sr FPGA Firmware Engineer – Applied Communication Sciences EMAIL: ad3ng3@r.postjobfree.com NO Relocation from Central New Jersey ... - Feb 15
... Tony Triolo: 732-***-**** Director (Immediate Supervisor) – Applied Communication Sciences Jim Hodge: 732-***-**** Sr FPGA Firmware Engineer – Applied Communication Sciences EMAIL: ad3ng3@r.postjobfree.com NO Relocation from Central New Jersey ... - Feb 15
Research Intern
New Brunswick, NJ
... Indian Space Research Organization(ISRO) January 2023 – June 2023 Research Intern Ahmedabad, Gujarat • Worked on implementing radar altimeter system using the FPGA platform provided by NanoXplore whose key feature is that it is Radiation Hardened. ... - Jan 15
... Indian Space Research Organization(ISRO) January 2023 – June 2023 Research Intern Ahmedabad, Gujarat • Worked on implementing radar altimeter system using the FPGA platform provided by NanoXplore whose key feature is that it is Radiation Hardened. ... - Jan 15
Design Engineer Electrical
Bayville, NJ, 08721
... Review design and test data then restructure FPGA (ALTERA Cyclone V) PLL, DDR3, Analog Sensors, LiPo charging/management system add adjusting termination and layers. New board passes FCC class A. June 2014 to July 2014 b. HD Video to Camera Link. ... - 2021 Apr 07
... Review design and test data then restructure FPGA (ALTERA Cyclone V) PLL, DDR3, Analog Sensors, LiPo charging/management system add adjusting termination and layers. New board passes FCC class A. June 2014 to July 2014 b. HD Video to Camera Link. ... - 2021 Apr 07
Engineer Jira
Somerset, NJ
... of Atomic Energy Project Overview: The objective of this project is to first interface the onboard General-Purpose Input Output (GPIO) like LED’S, Dip Switches, Push buttons available in the Spartan 3AN FPGA platform, and then interface the onboard ... - 2020 Dec 08
... of Atomic Energy Project Overview: The objective of this project is to first interface the onboard General-Purpose Input Output (GPIO) like LED’S, Dip Switches, Push buttons available in the Spartan 3AN FPGA platform, and then interface the onboard ... - 2020 Dec 08
Software Engineer
Belmar, NJ
... University of San Carlos, Cebu City, Philippines Bachelor of Science in Computer Engineering (Major in Digital Systems Design) Apr 2008 – Apr 2012 Magna cum laude – Dean’s List, 4 years, US GPA Equivalent: 3.8 Thesis: An FPGA-Based Cebuano Text-to ... - 2018 Aug 08
... University of San Carlos, Cebu City, Philippines Bachelor of Science in Computer Engineering (Major in Digital Systems Design) Apr 2008 – Apr 2012 Magna cum laude – Dean’s List, 4 years, US GPA Equivalent: 3.8 Thesis: An FPGA-Based Cebuano Text-to ... - 2018 Aug 08
RF test Engineer
New Brunswick, NJ
... This was implemented using FPGA (Field Programmable Gate Array), design using Verilog, and verified it using test bench consisting of clock generator, reset control, enable control and monitor/checker logic. •Domotics: Detailed project on Home ... - 2017 Feb 11
... This was implemented using FPGA (Field Programmable Gate Array), design using Verilog, and verified it using test bench consisting of clock generator, reset control, enable control and monitor/checker logic. •Domotics: Detailed project on Home ... - 2017 Feb 11
Network Management
North Brunswick Township, NJ
... Using Verilog HDL programming language high performance floating point adder/subtractor is implemented which occupies less area and targeted in Virtex-6 FPGA. Design achieves 331.939 MHz frequency. Published Paper : My project had published in ... - 2015 Nov 25
... Using Verilog HDL programming language high performance floating point adder/subtractor is implemented which occupies less area and targeted in Virtex-6 FPGA. Design achieves 331.939 MHz frequency. Published Paper : My project had published in ... - 2015 Nov 25
Engineer Engineering
West Windsor Township, NJ
... PROGRAMMING & SOFTWARE EXPERIENCE Languages: C / C++ / C#, Python, Java, Micro-C, Assembly, FPGA (VHDL/Verilog), ARM Assembly Language Software: CadSoft EAGLE PCB Design, ORCAD PCB Design, Proteus Simulation, NI Multisim & LabVIEW, MATLAB, Arduino, ... - 2015 Feb 15
... PROGRAMMING & SOFTWARE EXPERIENCE Languages: C / C++ / C#, Python, Java, Micro-C, Assembly, FPGA (VHDL/Verilog), ARM Assembly Language Software: CadSoft EAGLE PCB Design, ORCAD PCB Design, Proteus Simulation, NI Multisim & LabVIEW, MATLAB, Arduino, ... - 2015 Feb 15
Software Engineer Project
Monmouth Junction, NJ
... Designed and implemented a Multi-threaded Algorithmic Trading (eTrading) system in C++ using Algo-Logic FPGA Middleware which will be fed data from the above liquidity risk system. . Involved in transition of the LRS 1.0 (Liquidity Risk System) ... - 2014 Jan 15
... Designed and implemented a Multi-threaded Algorithmic Trading (eTrading) system in C++ using Algo-Logic FPGA Middleware which will be fed data from the above liquidity risk system. . Involved in transition of the LRS 1.0 (Liquidity Risk System) ... - 2014 Jan 15
Project Engineer
Bayville, NJ
... TECHNICAL SKILLS: Software’s PSPICE, XILINX ISE, MATHCAD, TEMS Hardware Kits XC3S400 FPGA, ATMEL AT89S52, 8086, 8051, 8251-USART Languages C, MATLAB, VHDL, VERILOG. Computer Skills Computer Hardware with troubleshooting, Windows 9x. IDE/Tools ... - 2012 Jun 27
... TECHNICAL SKILLS: Software’s PSPICE, XILINX ISE, MATHCAD, TEMS Hardware Kits XC3S400 FPGA, ATMEL AT89S52, 8086, 8051, 8251-USART Languages C, MATLAB, VHDL, VERILOG. Computer Skills Computer Hardware with troubleshooting, Windows 9x. IDE/Tools ... - 2012 Jun 27