| Job alert | Jobs 1 - 10 of 14 |
Mixed Signal Verification Engineer
Everest Consultants, Inc.
–
Hillsboro, OR
... Cadence Virtuoso, Xcelium, AMS-Designer, Verilog-AMS, and Spectre). Experience with SerDes is required We will consider digital verification engineers with 4+ years of UVM experience that are interested in mixed signal verification. Experience with ... - Apr 26
Lead RFIC Design Engineer
Everest Consultants, Inc.
–
Hillsboro, OR
... Matlab, Verilog-AMS, etc.). Experience designing in a mixed signal environment. - May 09
Semiconductor Senior Consultant
HCLTech
–
Hillsboro, OR
... Verilog or Verilog-A modeling proficiency is a plus. Any exposure to PLM tools would be plus. - Apr 21
Digital Verification Engineer
Skyworks
–
Hillsboro, OR
... Qualifications 6+ years (BSEE), 2+ years (MSEE) or 0+ years (Phd) of relevant industry experience Experience with system-level verification in ASICs Experience in implementation with Verilog and System Verilog Experience in post-processing with ... - May 09
Product Owner / Senior Consultant-w2
Tekvivid Inc
–
Hillsboro, OR
USD / Hourly
... Verilog or Verilog-A modeling proficiency is a plus. Any exposure to PLM tools would be plus - Apr 19
Mixed Signal Design Engineer
Snapchat
–
Esther Short, WA, 98660
... Experience with analog behavioral modeling using Verilog-A and real number modeling. A deep understanding of reliability issues and layout effects, such as electromigration (EM),and strategies to mitigate them. Minimum Qualifications: BSEE or ... - Apr 21
LTD Collateral Test Engineer
Intel
–
Hillsboro, OR
... Expertise in System Verilog using OVM (open validation methodology) or UVM (universal validation methodology) methodology Simulation and validation experience with hardware description languages such as Verilog and/or System Verilog Hands-on ... - Apr 16
SoC Verification Engineer - Pre-Silicon Power Management Validation
Intel
–
Hillsboro, OR
... Minimum 3 years' experience working on Power Management IP, PM Firmware, or PM SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM Minimum 3 years' experience with writing validation plans and software to implement ... - May 06
RTL and Verification CAD Engineer
Intel
–
Hillsboro, OR
... 3+ years’ work experience with one or more of the following: Hardware description languages (Verilog, System Verilog) and RTL/Validation tools (VCS, Questasim etc) Software engineering, Dev-Ops, machine-learning. 3+ years’ work experience ... - May 10
SoC Logic Design Engineer
Intel
–
Hillsboro, OR
... or CpE/Computer Engineering equivalent degree and 2+ years of experience in: Micro-architecture RTL development System Verilog Networking or IO integration Computer Architecture, Microprocessor or Chip-set design methods Preferred Qualifications ... - Apr 12