Semiconductor Senior Consultant

HCLTech is a global technology company, home to 211,000+ people across 52 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals including Financial Services, Manufacturing, Technology and Services, Telecom and Media, Retail and CPG, Life Sciences and Healthcare and Public Services. Consolidated revenues as of 12 months ending June 20, 2022 totaled $11.8 billion. To learn how we can supercharge progress for you, visit hcltech.com.

HCLTech is looking to hire Semiconductor Senior Consultant to support PLM Teams. This position requires the selected candidate to work from Hillsboro, OR with no provision for Hybrid working options.

Detailed description/responsibilities:

We are looking for an enthusiastic candidate for the position of Semiconductor Design expert Engineer to support PLM( product life cycle management ) team to use their knowledge of design high-speed analog circuits in mixed-signal ASICs, test chip and foundation IP development on latest technology nodes to help building PLM solutions for semiconductor companies. We are looking for a candidate with CMOS design, modeling, and layout experience who has successfully taped-out several ASIC, IPs and test chip designs.

Knowledge required in the areas like:

Develop detailed circuit specifications for mixed-signal circuits.

Design circuit architectures and transistor-level topologies to meet performance requirements.

Provide guidance for physical implementation (layout) of high-speed circuits.

Optimize circuits via simulation (using Cadence EDA tools) across various process and operating conditions.

Create cell/libraries models to be used for high level integrated functional and timing verification.

Integrate circuit elements into large analog/mixed-signal ASICs.

Participate in the characterization and testing of ASICs.

Help build test chip and validate.

Have good understanding of PDK and various components within PDK.

Skills:

Involved in all phases of multiple IC developments, from specification to product introduction.

Thorough knowledge of high-frequency, broad-band Analog Mixed-Signal IC design, covering both electrical and physical aspects.

Expertise in chip top-level logic and physical design, specializing in timing-aware logical partitioning, floor planning, and fast timing closure for mixed-signal chips.

Proficient in analog and mixed-signal modeling and verification for complex ICs, emphasizing functional and timing models as well as physical abstraction generation.

Solid understanding of Cadence RTL/STA/SDF gate-level verification flows.

Experience with standard and custom cell/IP cell library build, characterization, quality assurance, and release processes.

Collaborated extensively with EDA vendors to enhance tools and design flows, including Hard IP integration methodology.

Skilled in IC characterization at high frequency circuits, using tools such as high-speed sampling oscilloscopes, spectrum analyzers, VNAs, and signal sources.

Desired experience in CMOS FinFET (16nm or lower) design.

Verilog or Verilog-A modeling proficiency is a plus.

Any exposure to PLM tools would be plus.