| Job alert | Jobs 71 - 80 of 471 |
Senior Design Verification Engineer
Mulya Technologies
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Bengaluru, Karnataka, India
... · Overall, responsible for verification of ASIC designs To include such things as: o Design Verification – Implement test benches in UVM and Sytem Verilog, run regressions at RTL and gate level, generate and report DV metrics with respect to bug ... - May 05
Senior Digital Design Engineer
Mulya Technologies
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Bengaluru, Karnataka, India
... Verilog is required and SystemVerilog is a must. What we would be happy to see: Experience in ARM processor, bus design, SoC integration, standard interfaces protocols and common IP blocks. Experience in design flows for simulation, synthesis, ... - May 05
DV engineer 5+yrs
Aiml Services Pvt Ltd
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Bengaluru, Karnataka, India
... Pair with similar domain specialists across other geographical locations on core technical initiatives Strong experience in digital verification and familiarity with industry-standard methodologies Proficiency in System Verilog TB, UVM Methodology, ... - Apr 27
Verification Engineer
Alp Consulting Ltd.
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VasanthaNagar, Karnataka, 560001, India
... Digital Design and Verification Verilog/System-Verilog Common Skills. Work from Office Full time - May 02
Senior Lead Design Engineer, RTL And Front-End Design
L&T Semiconductor Technologies
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Bengaluru, Karnataka, India
... Experience and knowledge of Verilog, System Verilog, C/C++, Shell. Good knowledge in scripting like Perl, TCL or Python is a plus. Proficiency in Metric Driven Verification concepts, functional and code coverage. Expertise in directed and ... - Apr 20
R&D Engineering, Sr Engineer
Synopsys
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VasanthaNagar, Karnataka, 560001, India
... Knowledge on Verilog, VHDL or other HDL languages would be plus. Full time - Apr 19
Post Silicon Validation Lead / Manager
Intel
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Sadduguntepalya, Karnataka, 560029, India
... SOC, specifically GPU Architecture Fundamentals Microarchitecture/RTL/Logic Development System Verilog, Verilog knowledge Debug of Microarchitecture/Simulation Experience with Emulation platforms, Logic Analyzers, Oscilloscopes, Scan dumps etc. Job ... - Apr 08
SOC Design Verification Engineer
UST
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Bangalore Urban, Karnataka, India
... plans and define SOC verification strategies Execute the verification plan by developing C/C++ test cases and System Verilog /UVM testbench components and by integrating 3rd party VIPcomponents Job Requirements: Masters/Bachelors in Electrical ... - Apr 16
Senior Engineer, ASIC Development Engineering
Western Digital
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VasanthaNagar, Karnataka, 560001, India
... Strong hands on experience in Verilog, System verilog and UVM. UVM testbench development to build a robust, scalable and efficient testbench. Experience in Integrating 3rd Party VIPs in Testbench. Hands on experience on ARM based SOC verification. ... - Apr 18
SoC Verification Engineer
ScaleFlux
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Bengaluru, Karnataka, India
... with AMBA bus protocols, system memory hierarchy, system debug infrastructure and multi-core SOC Strong experience with Verilog, SystemVerilog, UVM and/or other Understanding of major SOC interfaces like PCIE, DRAM, Flash, I2C, SSP, UART is ... - Apr 30