Senior Lead Design Engineer, RTL And Front-End Design

Role - Senior Lead Design Engineer, RTL And Front-End Design

Stream - Customer Focused Product Development for Mobility, Industrial, Energy & Telecom

Reporting To - Chief Development Officer / Global Head of Engineering

Location -Bengaluru

COMPANY DESCRIPTION

L&T Semiconductor Technologies (LTSCT), a fully owned subsidiary of L&T, is the first major Indian Semiconductor product company - a fabless company for designing & delivering Smart Devices for Global Customers. A company that provides Semiconductor Devices and Technology partnerships by helping customers realise energy efficient, high-performance systems to benefit from data, electrification and software defined technology trends.

Harnessing the engineering mastery of L&T, LTSCT is forging a path to a world-class semiconductor ecosystem rooted in India. We aim to rewrite the rules of cutting-edge technology through relentless innovation to foster a vibrant culture of ingenuity, fuelling progress on every chip.

We have a presence in four prominent geographies i.e. US, Europe, Japan and India, with offices in Austin, Munich, London, Tokyo, Bangalore and Chennai.

JOB DESCRIPTION

LTSCT’s Chief Development Organization and Global Engineering team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for LTSCT's Automotive, Industrial, Energy and Telecom infra business lines. The team is challenged to produce industry-leading solutions covering very cost-sensitive, low power devices to highly integrated, high performance, multi-domain devices compliant with the latest automotive and industrial safety and security standards.

AREAS OF RESPONSIBILITY:

Contribute to the RTL delivery for a multitude of projects.

Work closely with system architects to define high level specifications that are implementable and robust, and Interface with verification/validation teams to ensure design quality and robustness.

Build strong collaboration with other R&D teams such as Verification, digital IP, Design Enablement, Emulation, and Validation to achieve project milestones.

Promote continuous improvement to design techniques to ensure ‘Zero Defect’ chips.

Collaborate with SME’s and key leaders in architecture, systems, emulation, SoC design, software, physical design, and IP teams developing key technical networks to influence.

Qualifications

At least 5+years of experience in related domains and have working knowledge.

Degree in Electrical Engineering or Computer Science, with 7+ years of experience on IP/Sub-System RTL Design.

Experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.

Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency.

Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers.

Experience and knowledge of Verilog, System Verilog, C/C++, Shell.

Good knowledge in scripting like Perl, TCL or Python is a plus.

Proficiency in Metric Driven Verification concepts, functional and code coverage.

Expertise in directed and constrained random methodologies.

Good knowledge of formal verification methodologies and assertions.

Experience with debugging of designs pre- and post-silicon, in simulation and on the bench.

Excellent written and verbal communication skills.

Experience with System Verilog and front-end tooling (simulation, waveform viewers, lint, CDC, RDC, etc.) is required, as well as highly efficient FE methodologies.

Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must.

Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems.