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ASIC RTL/SoC Design Engineer
TetraMem INC
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Fremont, CA, 94539
... Qualifications MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design Experience with Verilog and system Verilog Experience with VCS, Verdi or other industry standard tools Experience with pre-layout ... - Jul 30
ASIC/SoC Design Verification Engineer
TetraMem INC
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Fremont, CA, 94539
... Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding. Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core. Experience in ... - Jul 30
ASIC Design Engineer
SK hynix memory solutions America Inc.
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San Jose, CA
... Responsibilities RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications. Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and Firmware teams to ensure design ... - Aug 12
ASIC/SoC Design Verification Engineer
TetraMem INC
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Fremont, CA, 94537
... Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding. Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core. Experience in ... - Jul 27
ASIC RTL/SoC Design Engineer
TetraMem INC
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Fremont, CA, 94537
... Qualifications MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design Experience with Verilog and system Verilog Experience with VCS, Verdi or other industry standard tools Experience with pre-layout ... - Jul 27
Design Engineer
Innogrit
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San Jose, CA, 95110
... Proficient with Verilog, SystemVerilog, and Python or Perl. Strong knowledge of micro-architecture design, function modeling, RTL coding, and SoC Integration. Good at multi-clock domain designs, timing analysis, and optimization. Experience in ... - Aug 12
Principal SerDes Design Engineer
Celero Communications, Inc.
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Irvine, CA
150k-250k
... What You Will Do: Define architecture, specifications, and circuit topologies for next-generation SerDes Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, ... - Aug 11
Design Verification Engineer - Interface IP
Etched
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San Jose, CA
150000USD - 275000USD per year
... Strong candidates may also have experience with Experience handling vendors and integration of IP/VIP’s UVM/System Verilog Benefits Medical, dental, and vision packages with generous premium coverage $500 per month credit for waiving medical ... - Aug 12
Design Verification Software Intern
Tenstorrent University
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Santa Clara, CA, 95050
... The person coming into this role will have opportunities such as: writing low-level RISC-V assembly, building complex low-latency multithreaded testbenches, database programming, software testing and release automation, verilog coding and ... - Jul 30
Sr./Staff /Sr. Staff Engineer, IP Design (ASIC)
SK hynix memory solutions America Inc.
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San Jose, CA
... Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition. Experience with Clock Domain Crossing (CDC), timing closure, synthesis flows or Gate Level Simulation(GLS). Preferred Qualifications Experience in PCle(Gen4/5 ... - Aug 12