| Job alert | Jobs 31 - 40 of 121 |
Senior Physical Design Engineer
ACL Digital
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Bangalore Urban, Karnataka, India
... ● Well versed with the timing closure (STA), timing closure methodologies. ● Good Understanding of DRC, LVS,ERC and PERC rule files for lower tech node layout verification. ● Experience in lower tech nodes (7nm). ● Good automation skills in PERL, ... - May 10
Physical Design Engineer
BITSILICA
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Bengaluru, Karnataka, India
Location: Bangalore/Hyderabad Experience: 5-12yrs Notice Period: Immediate to 15 Days Primary Skills : Physical Design, CTS, STA & Physical Verification · Experience on RTL2GDS Implementation i.e. Synthesis, Floor planning, Placement, CTS, Routing, ... - May 17
Physical Design Engineer
DPIIND
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Bengaluru, Karnataka, India
... expertise on low power methodology in FinFET design, shared NWELL methodology is highly desirable Experience in Cadence design flow is highly desirable/flat and hierarchical flow/STA timing signify/PV and PI signoff/ multi-bit flops/Retention flops - May 08
Lead DFT Engineer
Tech Mahindra
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Bangalore Urban, Karnataka, India
... DFT mode STA and timing closure support - Apr 23
Physical Design Engineer
Synapse Design Inc.
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Bengaluru, Karnataka, India
... (power gating, multi-Vt, voltage islands, dynamic voltage scaling, body biasing, etc) is a plus Hands on experience with STA, DRC/LVS, LEC Experience in IR drop analysis is a plus Programming experience in Tcl, Perl is a plus Involvement in flow ... - Apr 24
Physical Design Engineer - Senior/Lead/Manager
THINSIL Technologies
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VasanthaNagar, Karnataka, 560001, India
... As a Physical Design Engineer, you will be responsible for tasks such as physical design, physical verification and STA. You will work closely with cross-functional teams to ensure the successful implementation of semiconductor designs. ... - May 07
Physical Design Engineer
Synapse Design Inc.
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VasanthaNagar, Karnataka, 560001, India
... (power gating, multi-Vt, voltage islands, dynamic voltage scaling, body biasing, etc) is a plus Hands on experience with STA, DRC/LVS, LEC Experience in IR drop analysis is a plus Programming experience in Tcl, Perl is a plus Involvement in flow ... - May 02
Physical Design Engineer
Cognitive Design Technology Pvt Ltd
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Bengaluru, Karnataka, India
... shared NWELL methodology is highly desirable Experience in Cadence design flow is highly desirable/flat and hierarchical flow/STA timing signify/PV and PI signoff/ multi-bit flops/Retension flops Job Type: Full-time Benefits: Health insurance ... - Apr 25
Support Back Office Sales
Aditya Birla Group
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VasanthaNagar, Karnataka, 560001, India
... Issuing Stock Transfer Advice (STA) for daily material movement from the plant to respective warehouses. Meeting day-to-day customer requirements, including dispatch notifications, Pre-Billed Not Delivered (PBND) and Delivered Not Billed (DBND) ... - May 12
SOC Clock Implementation
Rivos
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VasanthaNagar, Karnataka, 560001, India
... development for high performance design Experience with clock tree synthesis flow Familiar with synthesis, place route, STA, Spice, and other related analysis/verification tool Strong knowledge of CMOS circuit, low power design, EM, IR, noise, ... - Apr 29