| Job alert | Jobs 61 - 70 of 473 |
Infra Systems Architect - Engineer Staff
Qualcomm Technologies, Inc
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VasanthaNagar, Karnataka, 560001, India
... arch evolution) Good communication and work with minimal supervision Collaborate with Perf, Design and System team stakeholders in developing solutions Experience with Verilog, logic design principles with timing, area and power implications. ... - Mar 29
Senior Lead Design Engineer, RTL And Front-End Design
L&T Semiconductor Technologies
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Bengaluru, Karnataka, India
... Experience and knowledge of Verilog, System Verilog, C/C++, Shell. Good knowledge in scripting like Perl, TCL or Python is a plus. Proficiency in Metric Driven Verification concepts, functional and code coverage. Expertise in directed and ... - Apr 20
Senior RTL Design Engineer
ACL Digital
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VasanthaNagar, Karnataka, 560001, India
... Should be proficient in Verilog. 2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus. 3. Should have experience using ASIC ... - Mar 29
RTL (FPGA Design)
Alp Consulting Ltd.
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VasanthaNagar, Karnataka, 560001, India
... • Experience with Xilinx/Intel (Altera) • Familiarity with high level programming languages like C/C++, System Verilog, Scripts (TCL, Python) – advantage • Experience with UVM verification flow – advantage. - Apr 01
R&D Engineering, Sr Engineer
Synopsys
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VasanthaNagar, Karnataka, 560001, India
... Knowledge on Verilog, VHDL or other HDL languages would be plus. Full time - Apr 19
SOC Design Verification Engineer
UST
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Bangalore Urban, Karnataka, India
... plans and define SOC verification strategies Execute the verification plan by developing C/C++ test cases and System Verilog /UVM testbench components and by integrating 3rd party VIPcomponents Job Requirements: Masters/Bachelors in Electrical ... - Apr 16
Post Silicon Validation Lead / Manager
Intel
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Sadduguntepalya, Karnataka, 560029, India
... SOC, specifically GPU Architecture Fundamentals Microarchitecture/RTL/Logic Development System Verilog, Verilog knowledge Debug of Microarchitecture/Simulation Experience with Emulation platforms, Logic Analyzers, Oscilloscopes, Scan dumps etc. Job ... - Apr 08
Senior Engineer, ASIC Development Engineering
Western Digital
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VasanthaNagar, Karnataka, 560001, India
... Strong hands on experience in Verilog, System verilog and UVM. UVM testbench development to build a robust, scalable and efficient testbench. Experience in Integrating 3rd Party VIPs in Testbench. Hands on experience on ARM based SOC verification. ... - Apr 18
ASIC Digital Design, Sr Engineer
Synopsys India Private Limited
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VasanthaNagar, Karnataka, 560001, India
... Key Qualification BS/MS in EE/EC with 4+ years of relevant experience in the verification of IP cores and/or SOC Must have proven experience in developing HVL (System Verilog/UVM) based test environments, developing and implementing test plans, ... - Apr 13
Design Verification Engineer Cadence
Alp Consulting Ltd.
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VasanthaNagar, Karnataka, 560001, India
... And Technical Skills Required 5 years of experience in Processor based full chip verification / IP Verification Knowledge of Verilog/System Verilog, digital simulation and debug Knowledge of HS/LS Protocols / Processor based SOC architecture and ... - Apr 06