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Principal Engineer, AI & ML Design Verification
SiMa Technologies
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San Jose, CA, 95110
203800USD - 315900USD per year
... Define and develop MLA test bench components using UVM & System Verilog. Develop and execute a test plans. Lead Code coverage reviews and closure. System Verilog Assertion functional coverage development and closure. Manage debugging of test and ... - Jul 19
Principal Engineer, Hardware Design
SiMa Technologies
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San Jose, CA, 95110
203800USD - 315900USD per year
... Develop high-quality, synthesizable RTL (Verilog/SystemVerilog), including custom logic, protocol adaptation, and data-path optimizations. Define block-level interfaces, microarchitectural trade-offs, and design specifications. Collaborate with ... - Jul 19
Emulation Engineer
Etched
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San Jose, CA
150000USD - 275000USD per year
... Proficiency with SystemVerilog and Verilog, including DPI-based interfaces. Experience with git-based development workflows and scripting (Python) for automation and flow development. Strong candidates may also have experience with Experience with ... - Jul 19
ASIC/SoC Design Verification Engineer
TetraMem - Accelerate The World
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San Jose, CA
... planning, coverage closure, testbench and testcases development for function/performance verification Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding ... - Jun 29
ASIC/SoC Design Verification Engineer
TetraMem - Accelerate The World
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San Jose, CA, 95112
... planning, coverage closure, testbench and testcases development for function/performance verification Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding ... - Jul 04
ASIC RTL/SoC Design Engineer
TetraMem - Accelerate The World
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San Jose, CA, 95112
... with emphasis on RTL/SoC/digital design Experience with Verilog and system Verilog Experience with VCS, Verdi or other industry standard tools Experience with pre-layout simulation and post-layout simulation Understanding of the design flow. ... - Jul 04
ASIC/SoC Design Verification Engineer
TetraMem INC
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Fremont, CA, 94537
... Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding. Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core. Experience in ... - Jul 14
Automation Engineer (Machine Design)
SIX SIGMA/Winslow Automation Inc.
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Milpitas, CA, 95035
90000USD - 130000USD per year
... Familiarity with low-level programming languages such as C, Rust, Verilog, or any assembly language is a plus. Familiarity with machine vision hardware (lights, cameras, lenses) and software (image filtering, object detection, measuring and gauging) ... - Jul 19
Design Engineer
Innogrit
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San Jose, CA, 95110
... Proficient with Verilog, SystemVerilog, and Python or Perl. Strong knowledge of micro-architecture design, function modeling, RTL coding, and SoC Integration. Good at multi-clock domain designs, timing analysis, and optimization. Experience in ... - Jul 19
Test Engineer
Link Consulting Services
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Santa Barbara, CA
96600USD - 128800USD per year
... Job Qualifications: Minimum of a Bachelor's Degree in Electrical Engineering and 5+ years of related experience in testing electronic hardware systems Familiarity with Verilog, Xilinx ISE, Quartus FPGA development tools Working proficiency in C#, ... - Jul 19