| Job alert | Jobs 51 - 60 of 1738 |
Mixed Signal Verification Engineer
Everest Consultants, Inc.
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Hillsboro, OR
... Cadence Virtuoso, Xcelium, AMS-Designer, Verilog-AMS, and Spectre). Experience with SerDes is required We will consider digital verification engineers with 4+ years of UVM experience that are interested in mixed signal verification. Experience with ... - Apr 26
Sr. IC Digital Verification Engineer
Monolithic Power Systems
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Glendora, NJ, 08029
... Essential Functions: UVM and System Verilog based Digital Verification environment definition and development. VIPs standardization, definition, development and documentation. Define VIP’s integration into the Project’s Digital Verification ... - May 16
Emulation Engineer
LanceSoft, Inc.
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Austin, TX, 78716
... • Bring up ML/AI applications in emulation Required Skills: • Good Experience (5+ years) with Emulation based Verification using : Cadence Palladium, Synopsys Zebu or Mentor Veloce • Solid programming skills in C/C++, Verilog, System Verilog, UVM, ... - May 23
ASIC FPGA Digital Design Engineer w/ Secret Clearance
Indotronix Avani Group
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Linthicum, MD, 21090
... Experience of System Verilog, Verilog and/or VHDL: 3. Experience of FPGA, ASIC: Roles and Responsibilities: As a Digital Design Engineer, you will have a challenging and rewarding opportunity to be a part of our Enterprise-wide digital ... - May 24
Jr. Physical Design Engineer
Monolithic Power Systems
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Glendora, NJ, 08029
... Experience with programming, scripting and automation languages like Perl/TCL/Unix/Python Strong technical abilities & understanding in these areas: Verilog/System Verilog coding. Synthesis, CTS, DFT, Extraction, and STA closure across multiple ... - May 16
DFT Engineer
Park Lane Recruitment Ltd
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Milpitas, CA
... PRIMARY SKILLS:Dft, Lbist, Mbist, Verification, Test, Verilog SECONDARY SKILLS:ASIC EMPLOYMENT TYPE:Full Time/Direct Hire LOCATION:Milpitas, California WORK EXPERIENCE (YEARS):8 15 REMOTE STATUS:Partially Remote CLIENT WILLING TO SPONSOR: NO PRIMARY ... - May 03
Design Verification Engineer
Avance Consulting
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Folsom, CA
Job Description Design Verification Engineer Work Location – Folsom, CA USA (1st Day onsite) (8-15 Years Experience) Key Responsibilities: Utilize hands-on experience in System Verilog, UVM, and Testbench development to facilitate the verification ... - May 23
RTL Design Engineer - Senior
US Tech Solutions
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San Jose, CA
... Responsibilities: · Knowledge of PCIe Gen5 and PIPE specification · Knowledge of ASIC development flows · Knowledge of system verilog · Multi-clock domain designs. · Design constraints for synthesis and static timing analysis. Experience: • 10+ ... - May 14
Associate Staff Electrical Engineer
Brookhaven Science Associates
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Upton, NY, 11973
... Required Knowledge, Skills, and Abilities: * Bachelor's degree in electrical engineering, computer engineering or related discipline * Experience with FPGA firmware development * Understanding of RTL languages such as VHDL/Verilog/SystemVerilog * ... - May 08
Digital Design Engineer
Acro Service Corp
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Linthicum Heights, MD
... product life cycle (requirements, design, implementation and test) of FPGA Design and/or ASIC Design • Knowledge of System Verilog, Verilog and/or VHDLste • An ACTIVE DoD Secret level or higher security clearance and ability to obtain SAP (Special ... - May 23