ASIC Design Engineer

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Utilize digital design background for logic implementation, RTL generation and RTL analysis. Define, implement and support code management for RTL static analysis workflows in front-end infrastructure. Write tools, such as Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) and Verilog RTL and Gate Linting to automate RTL generation and verifying RTL. Perform automation using Perl, Python and TCL to streamline processes for generating RTL and verifying the designs in Front-End. Build and maintain restricted vendor environment within Apple to provide design data and get support from vendor and provides customer support. Track flow, tool bugs as well as support issues from the Front-End design community and share feedback to them. Root cause, debug and provide workarounds and solutions to RTL analysis flow related issues. Participate in coding and software development for RTL analysis and RTL construction flows. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $151,091 - $220,900/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Master’s degree or foreign equivalent in Electrical, Electronics or Computer Engineering, Computer Science or related field.

Experience and/or education must include:

Utilizing programming language (Python, Perl, or TCL) for building front-end flows used in RTL generation, RTL verification, RTL analysis and design integration

Utilizing RTL, Gate, and DFT Linting tools and techniques, and knowledge of System Verilog standards to design SoC along with building and maintaining Front-End flow using Perl and Python

Debugging software and RTL using an interactive debugger, including IntelliJ, VSCode, Gvim or Emacs, to triage and root cause issues

Experience operating in Linux OS, database technologies, revision control systems and virtual environments

Experience with ASIC clock methodology and tracing logic fan-in and fan-out of RTL and gate-level designs

Experience using regular expressions for writing scripts that can parse or process data from log files generated by Front-End flows

Experience with Front-End design concepts and tools including Static Timing Analysis or Primetime or Xcelium or VC Static

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