| Distance: | Job alert | Jobs 31 - 40 of 1067 |
CAD Engineer - RTL Construction
Apple
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Cupertino, CA
$147,400-$272,100/year
... Minimum requirement of Bachelors Degree +3 years of relevant industry experience Experience in programming languages such as Perl or Python Experience in Verilog/System Verilog Demonstrated experience driving large-scale software system development ... - Jul 06
SoC Design Engineer
Steinman Recruiting Associates
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Santa Clara, CA, 95050
$180000 - $220000 / yr
... System Verilog. Highly Desirable: PhD/MS Chiplet technologies (2, 3, 5 nm). Work experience in design services. 2-3 of the following: CPU (preferably, ARM and/or RISC-V), or GPU, or DSP; SoC Memory hierarchy; NoC -Fabric; low-power design and ... - Jul 09
Mixed-Signal IC Design Engineer
Apple
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Cupertino, CA
$181,100-$318,400/year
... test plans, optimize production testing, and debug sources of low-DPPM parametric yield loss Experience in C / MATLAB / Verilog modeling Proficiency in Python programming Experience with AI/ML, especially in applying tools and technique to any/all ... - Jul 06
GPU Design Engineer Memory Hierarchy
Apple
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Santa Clara, CA
$126,800-$190,900/year
... Knowledge of logic design fundamentals Knowledge of computer architecture fundamentals Proficiency in Verilog/System Verilog and HDL Minimum of BS degree Experience and knowledge of CPU or GPU architecture Knowledge in one or more areas of cache ... - Jul 06
Staff Firmware/Embedded Systems Engineer
Empower Semiconductor
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San Jose, CA
... Familiarity with Verilog and System Verilog models would be an advantage Experience with software configuration management tools, defect tracking tools, and peer review processes. Good communication skills in verbal and written form Strong sense of ... - Jul 15
DDR Mixed Signal Circuit Design Engineer
Apple
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Cupertino, CA
$147,400-$272,100/year
... Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able to collaborate with logic design team. Solid understanding of Circuit Verification tools (Simulators, Extraction, EMIR, Noise, SigEM, etc.). Generate block/chip level ... - Jul 06
Engineering Design 3
Belcan
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Harrisburg, PA, 17124
... Knowledgeable in VHDL, Verilog or System Verilog RTL coding and highly proficient in DFT methodologies. Responsible for operating in a team environment and collaborating across the different teams as required to accomplish the goals. Qualifications: ... - Jul 17
SoC Design Engineer
Omnivision Technologies, Inc.
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Santa Clara, CA
... design flow: coding, simulation, synthesis, static timing analysis, formality verification, DFT, using Simvision, EDA tools such as Prime Time, cadence Virtuoso, Design Compiler, Integrator, and Verilog and System Verilog programming languages etc.; ... - Jun 25
Cellular ASIC Design Integration Engineer
Apple
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Sunnyvale, CA
$147,400-$272,100/year
... Knowledge of RTL design and HDL languages (Verilog, System Verilog, etc.) Analytical skills to be able to make design tradeoffs for best performance, low area, and low power. Experience in driving power improvements based on power analysis tools ... - Jul 06
Analog Design Engineer
Jobot
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Alpharetta, GA, 30004
... Apply knowledge of SystemVerilog, PMIC, Verilog A, Virtuoso, Calibre, and Spectre in the design and development process. 3. Collaborate with cross-functional teams to define product specifications. 4. Conduct design verification and validation, ... - Jul 15