| Distance: | Job alert | Jobs 11 - 20 of 1882 |
Senior System Integration Engineer (Teradyne, North Reading)
Teradyne, Inc.
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North Reading, MA, 01864
... Familiarity with Verilog, System Verilog, UVM, VHDL preferred. * Operating Systems: Windows, Linux * Development Tools: Microsoft Visual Studio, GIT, Clearcase/Version Vault, JIRA * Excellent troubleshooting, debugging, and problem solving skills. * ... - Sep 30
Embedded Software Design Engineer (Semi Test Engineering North
Teradyne, Inc.
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North Reading, MA, 01864
... * Embedded software development in Linux environment * Software development using C/C++ programming languages * Csh, Python, Perl or similar scripting languages * Microcontroller design * Digital logic design * Verilog and/or System Verilog HDL ... - Sep 30
System Integration Engineer (Teradyne, North Reading)
Teradyne, Inc.
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North Reading, MA, 01864
... Familiarity with Verilog, System Verilog, UVM, VHDL is a plus. * Operating Systems: Windows, Linux * Development Tools: Microsoft Visual Studio, GIT, Clearcase/Version Vault, JIRA * Excellent troubleshooting, debugging, and problem-solving skills. * ... - Sep 30
Senior Quantum Embedded Engineer
Quantum Circuits
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New Haven, CT, 06501
... The ideal candidate will have extensive experience with Python, System Verilog for synthesis and simulation, AMD Xilinx RFSoC, mixed signal processing, and system architecture design. Candidates should have a proven track record of tackling ... - Oct 06
DFT Engineer Intern
Ambarella
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Manhattan, NY, 10017
... fault coverage * Timing analysis for DFT Modes Minimum Requirements: * MSEE in Electrical / Computer Engineering * Knowledge of DFT fundamentals * Knowledge of Logic design & Static timing analysis * Knowledge of Verilog and any scripting language - Sep 30
Engineer, Senior
ACL Digital
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San Jose, CA, 95111
... test plan for quality Verification Preferred Qualifications Experience with various aspects of digital verification such as test automation, code and functional coverage, constraint randomization, system Verilog assertions, and performance. ... - Sep 30
Graphics (GPU) Architectural Modeling Engineer
Apple
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Austin, TX, 78703
... + Experience with HDLs, Verilog, System Verilog or VHDL. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, ... - Sep 30
Graphics FE Implementation Engineer
Apple
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Austin, TX, 78703
... **Minimum Qualifications** + Experience with physical synthesis, including logic and PPA optimization techniques + Experience with Verilog, System Verilog or other scripting languages + Experience using logic equivalence tools for RTL and Gate-level ... - Sep 30
Floating Point Logic Design
Rivos
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Imperial, CA, 92243
... Knowledge of System Verilog Experience with simulators and waveform debugging tools Knowledge of logic design principles along with timing and power implications Understanding of low power microarchitecture techniques Understanding of high ... - Oct 18
Senior Member of Technical Staff
Rivos
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Austin, TX
... The design cycle will start with synthesis of various hierarchies to translate a High Level Description Language view of the functionality (Verilog RTL) into a Gate Level Description (Verilog netlist). Take the netlist through the various steps of a ... - Oct 18