Engineer, Senior

Job Responsibilities Own verification for various blocks in a SoC, sub-system or an IP and meet coverage goals Own the test-bench and enable reuse of block level UVM test-benches at sub-system and SOC level.

Come up with a comprehensive verification strategy encompassing simulations, formal verification, HW/SW reuse and simulation performance.

Work with cross functional IP teams for Integration verification Work with design team to understand Specifications and come up comprehensive test plan for quality Verification Preferred Qualifications Experience with various aspects of digital verification such as test automation, code and functional coverage, constraint randomization, system Verilog assertions, and performance.

Experience with Verilog/System Verilog, digital simulation.

Experience with Perl, Python, or similar scripting language.

Exposure to UVM is desired.

Experience with AMBA bus protocols Knowledge of low power design concepts and power management is a big plus.

Strong problem-solving ability Strong team player and communicator Comments for Suppliers: Need support with RFA DTOP feature verification by re-using or updating existing UVM Test bench Should have Good debugging skills Should have prior experience with System Verilog Assertions and Code/Functional Coverage Experience with scripting language like Perl, Python Good communication and Problem solving capability so as to interact with Design Team to understand specifications and come up with comprehensive Test plan for quality verification