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VLSI design & Verification Engg.

Company:
smartchipdesign
Location:
Bengaluru, Karnataka, 560001, India
Posted:
November 06, 2016
Description:

Job Description: The projects are for Design/Verification of IP/FPGA/ASIC/SOC

Skills Required:

The Skills required are minimum 2 years of experience in Verification, Verification Methodologies, EDA tool flow and also ablity to work in team with proactive thinking. The Design Languages are VHDL, Verilog, SystemVerilog, SystemC, C/C++, Verification Languages are e, SystemVerilog and verification methodologies, OVM, UVM.

verilog, systemverilog,ovm,uvm,axi verification, physical design, back end,front end, vlsi, asic design, asic verification