| Resume alert | Resumes 61 - 70 of 311 |
VLSI, Verilog, Data analytics, internship at ONGC
New Delhi, Delhi, 110075, India
... [4 weeks, July 2017 - August 2017]: Completed a practical training with main focus on Very Large Scale Integration (VLSI) and Verilog Hardware Descriptive Language on Xilinx platform. Gained hands-on experience in working with Field Programmable ... - 2018 Oct 27
... [4 weeks, July 2017 - August 2017]: Completed a practical training with main focus on Very Large Scale Integration (VLSI) and Verilog Hardware Descriptive Language on Xilinx platform. Gained hands-on experience in working with Field Programmable ... - 2018 Oct 27
Engineer Engineering
New Delhi, Delhi, India
... EVENT" 2) Certificate of completion in programing in C at Computer Education Council,Patna 3) Certification of participation in workshop on VLSI & EMBEDDED System Date : 4 june 2018 Place : New ashok nagar,Delhi INDUSTRIAL TRAINING Nutek india Pvt. ... - 2018 Jul 28
... EVENT" 2) Certificate of completion in programing in C at Computer Education Council,Patna 3) Certification of participation in workshop on VLSI & EMBEDDED System Date : 4 june 2018 Place : New ashok nagar,Delhi INDUSTRIAL TRAINING Nutek india Pvt. ... - 2018 Jul 28
Engineer Power Plant
Gurugram, HR, India
... Automation and Process Control: PLC, SCADA, VLSI, Embedded System, Pneumatics and Hydraulics, HMI. STRENGTHS: Strong analytical, problem-solving and conceptual skills. Strong Communication Skills. Ability to work under pressure and meet tight ... - 2018 Jun 07
... Automation and Process Control: PLC, SCADA, VLSI, Embedded System, Pneumatics and Hydraulics, HMI. STRENGTHS: Strong analytical, problem-solving and conceptual skills. Strong Communication Skills. Ability to work under pressure and meet tight ... - 2018 Jun 07
Engineering Fresh Graduate
Gurugram, HR, India
... Ltd., Gurgaon Project Title :- Telecommunication [SCTF] Duration :- 4 months VLSI Design & Verification Training using Verilog Hdl [25 June-28 june.2013] from Incise Infotech, Noida Company Name Huawei Technologies Co. Ltd Project Title ... - 2018 Apr 15
... Ltd., Gurgaon Project Title :- Telecommunication [SCTF] Duration :- 4 months VLSI Design & Verification Training using Verilog Hdl [25 June-28 june.2013] from Incise Infotech, Noida Company Name Huawei Technologies Co. Ltd Project Title ... - 2018 Apr 15
team player, matlab, embedded system, ms office
Noida, UP, India
... EDUCATION: B.TECH, Electrical and Electronics Engineering AWARDS &DISTINCTION Certification in the field of Embedded and VLSI design from IOTACELL. Participation certificate for workshop on MATLAB . AMCAT Certification TRAININGS PROJECTS More of ME ... - 2018 Apr 12
... EDUCATION: B.TECH, Electrical and Electronics Engineering AWARDS &DISTINCTION Certification in the field of Embedded and VLSI design from IOTACELL. Participation certificate for workshop on MATLAB . AMCAT Certification TRAININGS PROJECTS More of ME ... - 2018 Apr 12
Fresher
New Delhi, DL, India
... AREAS OF Analog/RF Mixed Signal Design FOCUS Digital System Design ASIC Design EDUCATION Master of Technology in VLSI Design (Jun 2011 – Jun 2014) Malviya National Institute of Technology, Jaipur GPA: 7.14/10.00 RF Integrated Circuits Analog and ... - 2018 Jan 30
... AREAS OF Analog/RF Mixed Signal Design FOCUS Digital System Design ASIC Design EDUCATION Master of Technology in VLSI Design (Jun 2011 – Jun 2014) Malviya National Institute of Technology, Jaipur GPA: 7.14/10.00 RF Integrated Circuits Analog and ... - 2018 Jan 30
Graduate Engineer in Electronics and Communication
Ghaziabad, UP, India
... Software skills: Basic C programming MATLAB and Simulink 8051 Microcontroller programming using Keil Cadence (to design VLSI circuits and analysis) Optsim(to design optical fibre networks) AWR Design environment Multisim 13(National Instruments) ... - 2017 Dec 02
... Software skills: Basic C programming MATLAB and Simulink 8051 Microcontroller programming using Keil Cadence (to design VLSI circuits and analysis) Optsim(to design optical fibre networks) AWR Design environment Multisim 13(National Instruments) ... - 2017 Dec 02
Training Industrial
DL, India
... Industrial Training in VLSI Design and Basics of SystemVerilog (FEBURARY 2017 – JULY 2017) Got training and hands on experience in bash scripting, tcl/tk, verilog, system verilog. Verilog based project - UART. 2. 6 week training of embedded C at ... - 2017 Jul 30
... Industrial Training in VLSI Design and Basics of SystemVerilog (FEBURARY 2017 – JULY 2017) Got training and hands on experience in bash scripting, tcl/tk, verilog, system verilog. Verilog based project - UART. 2. 6 week training of embedded C at ... - 2017 Jul 30
Electrical Engineering Information Technology
DL, India
... term course: ISTE Short Term Training Programme (STTP) on " Two-Week ISTE STTP on CMOS, Mixed Signal and Radio Frequency VLSI Design " 30th January, to 4th February, 2017 Conducted by IIT Kharagpur under the National Mission on Education through ... - 2017 Jul 27
... term course: ISTE Short Term Training Programme (STTP) on " Two-Week ISTE STTP on CMOS, Mixed Signal and Radio Frequency VLSI Design " 30th January, to 4th February, 2017 Conducted by IIT Kharagpur under the National Mission on Education through ... - 2017 Jul 27
software engineer
New Delhi, DL, India
... EXTACURRICULAR ACTIVITIES Visited Construction of Transformer from Thapar University, Patiala Actively participated in Quiz and Competitions at school and college level EDUCATION M.Tech (VLSI) from TIET (Thapar University), Patiala in 2014 B.Tech ... - 2017 Jun 18
... EXTACURRICULAR ACTIVITIES Visited Construction of Transformer from Thapar University, Patiala Actively participated in Quiz and Competitions at school and college level EDUCATION M.Tech (VLSI) from TIET (Thapar University), Patiala in 2014 B.Tech ... - 2017 Jun 18