VLSI verilog, VHDL, system verilog, STA, Synopsys EDA tools used

SHRADDHA AGARWAL

Bachelor in Engineering (ECE)

Address: ***/***, *** ****, *************, 100 ft Road, Indiranagar, Bangalore – 560038

E-mail: zxy12w@r.postjobfree.com

Mobile: +91-776*******

OBJECTIVE

To build a career with a dynamic and professionally managed organization that provide ample opportunities for growth in the field of VLSI design so as to reflect high standard of performance in all assignments, thereby ensuring organizational and personal growth.

INDUSTRY EXPERIENCE

Advanced Diploma in ASIC Design [ADAD] – (July 2010 – Jan 2011) from RV-VLSI Design Center,Bangalore.

Worked with BLUEBERRY CHIP DESIGN SERVICES PVT. LTD.,Bangalore as Design & Verification Engineer for 3 months (Jan 2011 – April 2011).

EDUCATIONAL PROFILE

Class University/ Institution/ Board Month & Year of Passing Percentage

B.E (ECE) Rajiv Gandhi Technical University,Bhopal,

Madhya Pradesh.

June, 2009 74.25%

I.S.C Delhi Board March, 2004 73.25%

I.C.S.E Delhi Board March, 2001 60.00%

SKILL SETS

Software Languages C, C++

Operating System Windows 95/XP, Linux

Hardware Description Languages Verilog, VHDL, System Verilog

EDA Tools Used QuestaSim 6.4b (Mentor Graphics)

Design Compiler (Synopsys)

Prime Time (Synopsys)

IC Studio (Mentor Graphics)

IC Compiler (Synopsys)

CORE COMPETENCY

o Good understanding of ASIC flow and IC fabrication process.

o Good in Digital circuit design, RTL design using VERILOG & VHDL.

o Good understanding of Synthesis, Static Timing Analysis, Floorplanning, Placement, Clock Tree Synthesis, Routing and Physical Verification.

PROJECT DETAILS & TRAINING

Blueberry Project:

o UART (Universal Asynchronous Reciever & Transmitter)

Objective: To write a synthesizable RTL code and Testbench.

Tool Used: QuestaSim (Mentor Graphics)

Challenges: FSM optimization, VHDL syntax, Debugging code for incompatible output

RV-VLSI Projects:

o Traffic Light Controller

Objective: To write a synthesizable RTL code

Tool Used: QuestaSim (Mentor Graphics)

Challenges: FSM optimization, Verilog syntax, Debugging code for incompatible output

o Physical Design of ORCA Chip

Objective: To learn the flow of chip-level design

Tool Used: IC Compiler (Synopsys)

Challenges: Placement of Macros, Clean DRC violations, Fixing PG connectivity

o Physical Design of I2C Block

Objective: To perform the block-level Floor planning, Standard cell placement and congestion analysis, Clock Tree Synthesis along with optimizations and Routing

Tool Used: IC Compiler (Synopsys)

Challenges: Removing floating shapes, Fixing DRC violations

o Inverter Design (Custom Flow)

Objective: To create the schematic of an inverter. Draw the layout following the design rules of Tower Jazz 180nm technology. Perform DRC & LVS and Parasitic Extraction.

Tool Used: IC Studio (Mentor Graphics)

Challenges: Layout drawing, Understanding foundry document, Debugging LVS errors

BE Projects:

o Automatic Lift Using Micro-controller (Major Project)

It is a two sensor, two floored microcontroller-based Automatic Lift. The microcontroller used is 89C51. There are two sensors comprising of basically IR LED and TSOP receiver. When someone comes near the sensor, the IR (Infrared) light is reflected back to the TSOP receiver which converts the IR light into data (a voltage signal) and is perceived by the microcontroller. The microcontroller was programmed to move the lift automatically towards the floor whose sensor had sent the data signal.

o Mobile Bug (Minor Project)

Mobile Bug is a handy pocket-size mobile transmission detector. It can sense the presence of an activated mobile phone from a distance of one and a half meters. So it can be used to prevent use of mobile phones in examination hall, confidential room etc. The moment the bug detects RF (radio frequency) transmission signal from an activated mobile phone, it starts sounding a beep alarm and the LED (light emitting diode) blinks. The transmission frequency of mobile phone ranges from 0.9 to 3 GHz with the wavelength of 3.3cm to10cm.

Trainings:

o Underwent 30 days of Industrial training program at BHEL, Jhansi on CNC (Computer Numerical Control) machine.

o Participated in a two days national level workshop on DIGITAL SYSTEMS AND VLSI DESIGN. This was conducted by electronics and communication engineering association (ECEA), in association with FEARBURSTER held at MANIT, Bhopal.

EXTRA CURRICULAR ACTIVITIES

o Won the Badminton tournament at district level.

o Runner-up in table tennis tournament at district level.

o Won table tennis, badminton, carrom, javelin, 400m relay race at school level.

o Stood 2nd in chess, volley ball, handball at school level.

o Stood 3rd in 200m race at school level.

PERSONAL DETAILS

Date of Birth : 12th JAN, 1986

Gender : Female

Nationality : Indian

Marital status : Unmarried

Father’s Name : Mr. M. R. Agarwal

Mother’s Name : Mrs. Surja Devi Agarwal

Languages known : English, Hindi

Passport No : H3181077

Permanent Address : 6, Jharkhariya Naria Bazaar, Jhansi - 284002

Date: 28-05-2011

Place: Bangalore (SHRADDHA AGARWAL)

__________

Contact this candidate