Design Engineer
Resume:
Curriculum Vitae
Sameer S. Shirgaonkar
Address: E-mail:
zttwqe@r.postjobfree.com
Flat No. 804, Building Wing - B,
zttwqe@r.postjobfree.com
Pristine Fontana, Near Maratha Mandir. Mobile: +91-
Bavdhan. Pune -411021
Date of Birth: 19th May 1977 Sex: Male Martial
Status: Married
Career Objectives:
To endeavor a challenging working position in which I can present my
innovative inspirations and create the valuable products. I would like
to utilize my knowledge to work as efficient Techno Manager.
Professional Summary of Major Experience:
Executive Summary:
Highly Committed, Proactive and Innovative Design Engineer with in depth
knowledge of FPGA & Large Scale Digital Mixed Signal Hardware & Circuit
Design, implementation and system validation. Quick to Assimilate new
concepts and cutting-edge technologies such as RTL coding styles for
improved synthesis QoR verification challenges.
I have around 11 yrs. & 7 Months of extensive experience in Research,
Development and Project Management with specialization in the field
Hardware, VLSI, as FPGA/ SOC / ASIC Design & Verification Engineer,
Xilinx/Altera, Hardware Architect, Design, Verification, and Silicon
Validation Engineer, for Multimedia & Wireless Networking Chip Design,
Digital & Analog PCB Board Level Design, Engineering Technology, Design
Methodologies, State of the Art Hardware Software Tools, Testing
Equipments, Flow, Process, Time-to-Market FPGA/SOC/ASIC.
As Hardware Architect & VLSI Front End Design, posses technical
background and know-how in leading development of high-performance and
low-power multi-processor SoCs, using system tools and languages like
VHDL, Verilog, C, Assembly language. Hardware Design of Electronic
Circuits, that includes Architecture Definitions along with complete RTL
flow of FPGA and ASIC, from logic building to board level design and
testing, Timing, STA and Verification for the Design, Efficient Memory
Management Digital Design, Micro-Controllers, Micro-Processors, ARM,
DSP. I have In-depth knowledge of various Processors Architecture,
Extensively worked on Firmware & Device Driver Development, Knowledge of
BSP Development, Use state of the art design, processes, and test
technology to address volatile market demand in the Verticals of
Wireless, Telecommunications, Networking, Consumer Electronics,
Automotive and Industrial Electronics Applications. Porting the
Algorithms on the FPGA for Target Tracking. DSP Implementation of the,
Motion Control, Auto Pilot & Flight Navigation Algorithm.
Extensive Experience in Hardware Design and Development of Defense,
Military and Avionics Air borne applications, Experience in FPGA Design,
Board Level Design including: design of board schematics, Layout,
components selection, defining routing and layout constraints, BOM, and
board manufacturing follow-up. Parallel interface, LVDS interface, UART,
SPI, SPORT, RS232, RS422, Interfaces. Experience in board design with
Defense systems high speed digital devices like FPGAs and DSPs. Sound
Knowledge in Analog Circuit Design, Operational Amplifiers, differential
converters, filters, ADCs, DACs, High Speed ADCs & DACs etc. Experience
in Power Supply Design (LDO, DC-DC converters). Two phase and three
phase BLDC Motor control.. Experience on Rigid and Rigid -Flex - Rigid
boards up to 10 layers. Board level debugging skills using digital multi
meters, DSO, MSO, logic analyzers, Chip-Scope. Good exposure to
certification testing like EMI-EMC, Burning Test, Thermal Shock and
Vibration.
Personal Skills:
Demonstrating a logical and analytical approach to complex problem
solving and issues. Highly motivated, self-starter that works well on
individual and team assignments. Thrive on challenges and work well
under pressure deadlines, while maintaining a good sense of humor. Have
progressively led both hardware and software engineering teams to
rapidly adapt, grow, and succeed through alignment of technology and
product development strategies with customers' needs in a timely manner
leveraging internal resources, outsourcing, and external partnerships. I
have strong analytical, design and team management skills. My key
strengths are Design Development, optimization and implementation of
VLSI based projects. Posses excellent written and verbal communication
skills. Met many project deadlines by using organizational and
interpersonal skills. It has always been my effort to contribute towards
the success and growth of the organization. Handled multiple clients
Independently by defining Stream Line Processes and Methodologies.
Achievements:
V Customer Satisfactions for Time Bound Quality Service and Delivery
V Published White Paper on Simulation of H.264/AVC Using VHDL in SPIT-
IEEE Colloquium and International Conference, Mumbai, India
V Xilinx XPERT Partnership Program & Cypress PSoC Consultant
Education
V Master of Engineering (ME) in Electronics and Telecommunication from
Mumbai University, India
V Bachelor of Engineering (BE) in Electronics from Mumbai University,
India.
V Diploma in Industrial Electronics from Board of Technical
Examinations, Mumbai, India
V Diploma in VLSI Design as a part of industrial training from
Knowledge Oak (I) Pvt. Ltd at CDAC ACTS, Mumbai, India.
V Attended training program in "Elements of Micro Electronics" from IIT
(Indian Institute Of Technology) Bombay.
V Attended 2nd Workshop on Design Verification Methodologies organized
by VLSI Society of India conducted at Wipro Pune.
V Attended training program in EmbeddedSystems from Keil Software Inc.
V Attended Workshop on Black Fin DSP of Analog Devices at IIT (Indian
Institute Of Technology) Chennai.
V Workshop in Embedded Systems and Digital Signal Processing, organized
by the Electrical Engineering Students Association (EESA) being held
in IIT Bombay
V Attended training program of the Xilinx Technical Knowledge Summit -
2011/2012
V PROMS Project Management Training from KPIT Cummins Infosystems
Technical Skills
|Operating |Windows XP/2000/7/NT |
|Systems | |
|Technologies |VLSI, Hardware Design & Embedded. |
|Languages |VHDL, Verilog, C, & Assembly |
|VLSI |Mentor Graphics Model SIM 6.3, Questa, Leonardo Spectrum,|
|Tools/Software |Precision RTL Synthesis, FPGA Advantage6.1, |
| |Synplicity7.71, ASIC Prototyping using Certify, Renoir |
| |for simulation and synthesis. Project Navigator Xilinx |
| |ISE, Xilinx EDK and FPGA Express For Implementation and |
| |Place & Route and Synopsys PrimeTime suite for Static |
| |Timing Analysis (STA). Xilinx Chip Scope a Real Time |
| |Debugger For FPGA, Like Logic Analyzer. Altera Max plus |
| |2, Quartus || Design Software. Cadence Inc, PSpice, |
| |Magic, IRSIM, Tanner, Micro Wind |
|Embedded |Keil Cross Compiler & Keil Real View for ARM, A51, S51, |
|Tools/Software |ASM51, ARM GNU Tool Chain, IAR, AVR, SPJ Compiler, |
| |Dynamic C, HEW Renesas for compiler assembler linker |
| |locater and debugger. |
|DSP |Xilinx System Generator Visual DSP 3.5/5.0(VDSP) Analog |
|Tools/Software |Devices, Texas Instrument Code Composer, NDK Philips |
| |Nexperia, |
|PCB |Cadence Orcad, Mentor Graphics, PADS, Board Station & |
|Tools/Software |Expedition. |
|Designing |Top Down & Bottom UP Design Approach, Modular Design, |
|Techniques |Dynamic Programming. |
|Project |Techno Commercial Proposals, Microsoft Project |
|Management |Planning/Tracking, Effort Estimations, Project |
| |Scheduling, People Management Resource Allocations and |
| |Configuration Management using Visual Source Safe, SVN &|
| |CVS, |
| |DRDO Tender Documentation Requirements & Design |
| |Documentations. |
Technical Expertise:
Hands on Experience:
FPGA SoC Hardware Architecture, Design, Verification, and Silicon
Validation Engineering Skills Development. FPGA Xilinx Virtex4/5/6 &
Spartan3/6 SoC Embedded Processor and IP Core Hardware Design, IP
Functional Block Design, Integration and Test, Embedded Software Design
Engineering Skills Development. Developed Technical skills in ABV for
Synthesizable RTL Coding VERILOG/VHDL and SystemVerilog Testbench
Environments, C/Assembly ISR's for Embedded High Performance Processors,
Synthesizable FPGA Testbench Architectures, and Standard ASIC Chip
Design Methodologies to facilitate Career Development focusing on a
Silicon Platform Architecture, Design, Verification, and Validation.
Developed skills as an FPGA SoC Architect, Design, Verification, and
Silicon Validation Engineer using Standard and Application-Specific
Embedded Processor Cores (x86, VLIW, SHARC SIMD & Multi-Core), DSP
Cores, ARM Cores, I/O Cores, Network Processor Architectures,
FPGA/ASIC/SOC Synthesizable ABV Design Verification Methodologies, and
FPGA/ASIC/SOC Technologies.
FPGA design and ASIC-Prototype system development Designed High-speed
SoC-prototype systems to demonstrate algorithms features on hardware
involving designing additional RTL blocks, creating an appropriate
verification environment and run basic tests to uncover early issues
then perform FPGA design flow using Xilinx with adapting IP models for
suitability, re-designed clocking modules, synthesis, performing static-
timing analysis and place-and-route. Experienced in debugging and
testing Hardware board using JTAG cable, Oscilloscope and Logic
Analyser. Experienced in device driver programming using C environment
in Linux to interact with Hardware.
Hands on with Standard Interfaces, MIL1553, IEEE 1149.1 JTAG, USB1.1,
USB2.0, USB Embedded Host, RS232, RS485, PCIe, PCI, Ethernet RMII/GMII,
I2C, SPI, CAN, SCCB(CMOS/CCD) MMC, SDIO & CF Interface, RF, ZigBee, GPS
Receiver, GSM GPRS, CDMA 1xRTT & EVDO, IEEE 802.11 b/g Wi-LAN. Memory
Interface Controller for SRAM, SDRAM, DDR SDRAM, QDR SDRAM
Hardware Execution Knowledge:
1. Complete understanding of the VLSI & Embedded Product Project Life
Cycle
2. Digital Hardware Design: Combinational and sequential circuit
design Synchronous and asynchronous circuits Common combinational
hardware building blocks gates, multiplexers, decoders,
adders/subtracters, PLDs, PLAs etc. Common sequential hardware
building blocks flip-flops, counters, registers, memories etc.
3. Advance Design Principles/Practices (Specification Description,
Documentation, Modeling and Analysis, Organized Hierarchical Top-
Down Approach, Design Entry, Logic Synthesis, Gate Switch and
Transistor Level Simulation, Cell Models, Static Timing
Analysis, Formal Verification, In-Circuit Verification).
4. FPGA (Logic Cell, LUT, Slices, Embedded Processors, DCM/DLL, IO
Cell Architecture, Multiple Clocks Domain, Interconnect and Design
Software of Xilinx and Altera).
5. FPGA Designing, FPGA Design Architecture and Functionality RTL
VHDL Coding, MTI Simulation, and Synopsys Synthesis, and Lab Debug
6. ASIC (Construction, System Partitioning, Floor Planning,
Estimations About Cell Areas And Delay Times, Standard Cell
Concept, Layout Design, Placement, Physical Design flow, Global
Clock, Detailed and Special Routing, Circuit Extraction).
7. CMOS (Processing Technology, Circuit Characterization and
Performance Estimation, Physical Design of Logic Gates, Clocking
Strategies, IO Structure, System Design and CMOS Testing).
8. HDL Soft & Hard IP Development for FPGA's, ASIC & System-On-Chip
Performance tested on Silicon. FPGA & CPLD worked on Xilinx (
Spartan, Spartan2/2E, Spartan3/3E/3A, VirtexE, Viretex2/2-Pro/4/5,
XC9500 & CoolRuner), Altera (Flex/Cyclone/Max II)
9. Performing Pre & Post Layout, Synchronous & Asynchronous Timing
Analysis for the FPGA, addressing timing closure in high-
performance applications. Input & Output Standards Mapping for
FPGA
10. Memory Management handling in FPGA using Internal Memories like
Block RAM & Distributed RAM along with External Memories like
SDRAM, QDR RAM, DDR SDRAM.
11. Embedded Systems Processor Architecture, Micro Processor & Micro
controller based Designing & Programming Assembly and C, Porting
Operating Systems & Board Support Package Customization for ARM
based Systems.
12. Firmware & Frameworks Development for Various Micro Processor &
Micro Controller. Remote Firmware Upgrade development for System
designs involving processors, on-board devices and external
interfaces. Multitasking Applications development Board support
packages that includes initialization routines, boot code, debug
utilities, Interrupt and error handlers. Hardware abstraction
layer for interoperability with kernels for operating systems.
Platform migration Processor architectures CISC to RISC
Micro-Controllers: - Intel, Philips NXP, Atmel, Renesas, Texas
Instruments, Microchip, Cypress.
Micro-Processor:- Rabbit, Xilinx Micro Blaze, Power PC, Altera
NIOS-II.
Multi-Core:- Dual and Quad core Processor, Multi Media Processor
DaVinci.
DSP:- BlackFin, Nexperia PNX, DM6446, DM355.
13. Algorithm designs, Data Structures: Stacks, Queues, Priority
Queues, Skip lists Searching Sorting Selection : QuickSort,
MergeSort, Graph Algorithm : Shortest Path Algorithms, Spanning
Tree Algorithms, Time and Space complexity of algorithms String
processing. Algorithm Design Methods : Greedy Method, Divide &
Conquer, Dynamic Programming. Programming Skills, Co -State
Implementation.
14. Domain Knowledge of Avionics Airborne & Defense Applications,
Guidance & Control Data Compression, Cryptography, Image
Processing, Audio Video Compression (JPEG, MPEG, H.263 and H.264),
Wireless Tele Communications, Networking, IEEE Standards.
15. Video Compression: Designed a video coding system based on block-
matching with a Wavelet& DCT-based compression of the Video
frames. Familiar with MPEGx/H.26x and other video compression
standards. Image Compression: Extended knowledge of lossless and
lossy still image compression techniques, including Subband and
Wavelet coding. Implemented a DCT-based still image compression
scheme similar to the JPEG standard.
16. Extensive Experience in Hardware Design and Development of
Military and air borne applications, Experience in board level
design including: design of board schematics, Layout, components
selection, defining routing and layout constraints, BOM, and board
manufacturing follow-up. Parallel interface, LVDS interface, UART,
SPI, SPORT, RS232, RS422, Interfaces. Experience in board design
with systems high speed digital devices like FPGAs and DSPs. Sound
Knowledge in Analog Circuit Design, Operational Amplifiers,
differential converters, filters, ADCs, DACs, High Speed ADCs &
DACs etc. Experience in Power Supply Design (LDO, DC-DC
converters). Two phase and three phase BLDC Motor control.
Experience on Rigid and Rigid -Flex - Rigid boards up to 10
layers. Board level Debugging Skills using digital multi meters,
DSO, MSO, logic analyzers, Chip-Scope. Good exposure to
certification testing like EMI-EMC, Burning Test, Thermal Shock
and Vibration.
17. Design, Development & Implementation of Hardware & Firmware
using, GPS Receiver Modules like GPS Receiver (uBlox, Falcom,
Telit, Siemens, Wavecom Navman, Trimble, GlobalSat & Analog
Devices). I have knowledge of the Sirf Star III High Performance
Chipset used in the GPS Receiver Computing the Locating from Solid
Angle and NEMA Protocol, Hot, Warm & Cold Start Very high
sensitivity (Tracking Sensitivity: -159 dBm). Hardware Design of
the GPS Receiver with RF Noise Handling. Debugging the issues
using Logic Analyzer & Oscilloscope for Noise Levels issues in
Hardware. Worked on GPSOne in CDMA Technology, Knowledge of WAAS &
DGPS Technology and Ionospheric disturbances, timing, and
satellite orbit errors
18. Design, Development & Implementation of Hardware & Firmware
using, GSM/GPRS/EDGE & CDMA/1xRTT/EVDO Modules like uBlox,
Siemens, Wavecom, Telit, Sony Ericsson, Fujitsu, & etc . I have
knowledge of the RF, Baseband Processing, Software Defined Radio,
High Performance Chipset used in the GSM/GPRS & CDMA Modules and
AT & ATi Command Protocol, Packet Switching, TCPIP, UDP, FTP,
Socket Communications, Working on the Application Layers, E-Mail &
SMTP. Hardware Design of the GSM/GPRS & CDMA Module with RF Noise
Handling. Debugging the issues using Logic Analyzer & Oscilloscope
for Noise Levels issues in Hardware. Knowledge of the BTS & MCS in
Mobile Architectures.
19. Implementation of application in FPGA, ASIC, CPLD, Micro Processor
and Micro Controller 8/16/32- Bit,, DPS & ARM with SRAM's SDRAM
interfaced with Ethernet and USB. Implementation of Audio/Video
Codec in Processors & FPGA with SDRAM, Camera (CMOS Image
Sensors), GPS Module, Multi Media Card interfaced with CF (Compact
Flash) on WinCE based PDA and SDIO (Secure Digital Input Output)
on Palm based PDA. The testing was based on GSM-GPRS, CDMA and Wi-
Fi networks.
20. Design various Multi Layer PCB under my guidance right from
component Identification (With Constrains like impedance matching,
Delays for signal and data also with LVDS signals), Circuit
Design, Schematic Entry, Library of Package Creation & Assigning,
Placement, Layout & Routing, Gerber generation. High Speed
Simulation, Signal Integrity & EMI EMC Analysis. After the PCB is
manufactured the BBT is done and Component's assembling and
soldering. Knowledge of BGA component and also sourcing component.
21. Extensive Experience for Hardware Testing using variety of Testing
/ laboratory Equipments such as Digital & Storage Oscilloscope,
high-frequency spectrum analyzers and signal generators, for
various low and high frequency parameters tests and measurements.
Xilinx Chipscope tools for Debugging the RTL Coding Logical
Problems
22. Extensively done the Environmental Stress Screening (ESS) &
EMI/EMC Testing for the Avionics Electronics Products . MIL
Standards Document followed for Qualification (MIL-E-5400, MIL-STD-
454, DOD-STD-100, MIL-I-46058, MIL-STD-1515, MIL-STD-130,MIL
704D/E, MIL-STD-461E, JSS-55555, MIL-STD-810F,MIL-H-5606E,OERD
2497/MIL-L-7808)
23. Technology Transfer to OEM's and Handling different Semiconductor
Vendors Distributors for Procuring Components and Negotiating and
Optimizing Bill of Material.
24. Product Designing with Design for Manufacturability aspect is
taken in to consideration while designing complete Systems.
Environmental Certifications (High Temp, Vibration, Burn in Test &
etc), CE/ FCC Certification Co-Ordination with the Agencies, also
considering the Certification aspect during Design.
25. Technical Documentation, Patent Document, Effort Estimations,
Techno Commercial Project Proposal, Preparing Project Plans,
Requirement and Specification Document, Time Lines. Test Plan &
Testing Strategy, Delivery Documentation, Product User/Operational
Manual, Case Studies, Product Brochures and Marketing Document.
Relevant Employment History:
KPIT Cummins Infosystems Ltd
Current Designation: - Solution Architecture
VLSI FPGA/ Hardware Design Engineer Pune July 2010 --
Currently Working
The semiconductor group at KPIT provides high quality design services
and IP & Product led solutions with a strong focus on Automotive,
Defense & Industrial Electronics domains. We work with 13+ OEM's, 31+
Tier1's and 7+ semiconductor companies to create differentiated
engineering solutions. A key differentiator is our Analog & Mixed signal
capabilities combined with the maturity in handling Digital & SOC
designs.
Iflect Technologies India Pvt Ltd
Current Designation: - Project Manager VLSI
VLSI / Embedded Design Engineer Mumbai April 2002 - July
2010
Iflect Technologies established Application Development services covers
the entire Hardware & Software Development Cycle, starting from the
devising of the Hardware Requirement Specification to realization of a
Physical product. Our project execution expertise with defined processes
and strong technical focus enables us to accomplish outsized
applications. Iflect is Working mainly on designs using FPGA's, CPLD,
ASIC, SoC, PSoC, Micro Processor, Micro Controller, ARM, DSP & for
porting application like Image Processing, Video Compression, Data
Compression and Cryptographic application on Wireless Technology.
Hardware Circuit Design & Development using FPGA's, CPLD, ASIC, SoC,
PSoC, Micro-controller, Micro Processor & DSP for Embedded Systems with
various interface for handheld like PDA Mobile Devices Smart Phones.
Audio Video Codec Accelerator cards with PCIe, PCI PLX, USB 2.0,
Ethernet, Giga Bit Ethernet, Wi-LAN, Wireless Technologies
GSM/GPRS/EDGE, CDMA, and GPS. USB2.0 based IEEE 1149.1 tools for
Programming and Boundary Scan Testing.
Knowledge Oak India Pvt. Ltd. (Sister Concern of Iflect Technologies
India Pvt Ltd)
VLSI Design Engineer Mumbai April 2001 -- April 2002
This company is in VLSI and Embedded systems applications for GSM/GPRS,
GPS, and Energy Meter. RF and IF based circuits of Power line. Power
Line Communication Carrier (PLCC) Module for Home networking.
Intern - High Energy Physics Department of Tata Institute of Fundamental
Research(TIFR), Mumbai, India.
Areas Of Specialization:
V Extensive Experience Modeling and Analysis with Organized
Hierarchical Top-Down Approach
V Extensive Experience in RTL Coding in VHDL, with complete suite of
FPGA/ASIC Design Flow.
V Experience in writing automated test bench's using VHDL and FLI along
with TCL/TK.
V Extensive Experience in Design, Implementation and verification
issues with Xilinx FPGA's.
V Extensive Experience on Porting Algorithms in HDL with RTL Design.
V Extensive Experience for writing memory interfaces in VHDL for SRAM,
SDRAM, QDRSRAM, DDR2, DDRSDRAM and NADN-Flash follows the JEDEC
Standards.
V Extensively working on the Pre & Post Timing Analysis, Static Timing
Analysis
V Extensively working for preparing User & Timing Constrains for
achieving the Performance
V Worked on Spartan-2/2E, Spartan-3/3A/3E, Vertex2, Vertex2 Pro,
Vertex4 & Vertex5 & Spartan 6 FPGA, Cool Runner, XPLA CPLD are From
Xilinx.
V Extensive Experience in Prototype Hardware Board/Circuit Design
(Wireless Technologies, RF Boards, Processing, Booting, Memory, Power
Supply Design, Battery charger, etc) and Real Time Testing.
V Experience in board level design including: design of board
schematics, Layout, components selection, defining routing and layout
constraints, BOM, and board manufacturing follow-up.
V Experience in hardware design and development of Military and air
borne applications
V Parallel interface, LVDS interface, UART, SPI, SPORT, RS232, RS422
Interfaces
V Experience in board design with systems high speed digital devices
like FPGAs and DSPs
V Sound Knowledge in analog circuit design, Operational Amplifiers,
differential converters, filters, ADCs, DACs etc.
V Experience in power supply design (LDO, DC-DC converters)
V Two phase and three phase BLDC Motor control
V 24 bit parallel LCD Interface, LCD power supply design
V Experience on rigid and rigid - flex - rigid boards up to 10 layers.
V Board level debugging skills using digital multi meters, DSO, MSO,
logic analyzers, Chip-Scope
V Good exposure to certification testing like EMI-EMC, Burning Test,
Thermal Shock and Vibration.
V Extensive Experience Design & Development of Firmware & Framework and
verification for 8/16/32 Bit Micro controllers, Micro Processor, ARM
& DSP
V Extensive Experience on Free RTOS, BSP Customization & Low Level
Device Driver & Developing Multitasking Applications
V Knowledge of Monitor Programs, ICE (In Circuit Emulators), ICD, GDB,
JTAG for Debugging.
V Extensive Experience in Airborne & Defense Applications, Multi Media,
Automotive, Wireless Networking & Cryptography
Roles & Responsibilities on different Projects:
Techno Managerial Responsibilities
V Preparing Effort Estimation & Project Scheduling with Resource
Utilizations
V Preparing Delivery & Acceptance Document
V Preparing Techno Commercial Project Proposal.
V Project Planning in MPP and Design Document with Acceptance Strategy and
Back up Plan.
V Preparing Requirement & Specification Document and Consolidating the
Specification with Multiple Client Interaction.
V Client Interaction Conference Calls for Ongoing Project Development and
Pre Sale Support for Marketing Team.
V Preparing High & Low Level Design Document as per the Specifications and
Applications.
V Preparing the Test Plan, Test Strategy and arrange for Test Setup and
have Test Environment.
V Managing Project Progress Report, Time Sheets with Efficient Resource
Management for Fixed or Time & Material based Projects.
V Configuration Management, Change Request, Data Management, Version
Management using Visual Source Safe VSS
Technical Design, Implementations Development & Testing Responsibilities
V Design & Defining the Architecture of System for Application with
considering the Processing Device.
V Analysis and Study of Image Processing, Audio Video Codec Algorithm.
Video Compression, Still Image Compression.
V Design & Development of Algorithms and Protocols for Communication &
Networking.
V Platform Evaluation for huge size Projects for Processor Selection.
V Hardware & Software Co Partitioning
V Design Memory Management depending on type of Application
V FPGA/CPLD/ASIC/SoC Design & Verification
V Designing, Implementing & Verifying RTL in Verilog/VHDL Coding, &
Functional Simulation.
V Code Coverage, Performance Analysis and Optimizing the Codes as per
Processing Device. Code Review and Code Documentations.
V RTL Logic Synthesis, module-level and top-level synthesis
V FPGA & ASIC Implementation (Translation, Mapping, Floor Planning,
Place and Route).
V Static Timing analysis, Timing closure knowledge for high speed
multiple-clock domain designs. Back Annotation, and Verification.
V Downloading the Code in the FPGA/CPLD, do the Real Time Testing
/Debugging using Hardware & Software Tools like Chipscope, Logic
Analyzer or Oscilloscope.
V Design & Verification issues for the FPGA Silicon Validation or ASIC
Prototyping for Multi Core ASIC.
V Design & Defining the Firmware, Frameworks & API. Mixed coding in C &
Assembly for Micro-Controller, Micro Processor, ARM & DSP with
Simulation, Compile & Debugging
V BSP and Driver Development for DSP Code Coverage and Performance
Analysis
V Component Identification based on various Parameters like (Electrical
Characteristics, Mil Grade, Form Factor, Delivery Time, JEDEC
Standard and Etc.) and Preparing Bill of Material
V Hardwar Design, Circuit Design, Schematic Entry, Net-list
Verification.
V Defining Power up Sequences, Booting Options, Multiple Devices
Programming, USB, Serial, Ethernet & GSM/GPRS
V Remote Firmware Upgrades using GSM GPRS
V Reverse Engineering of Systems in Hardware & Firmware.
V PCB Design : Library of Package Creation & Assigning, Board Layout &
Multi Layer Stack Defining, Placement, Layout & Routing, Gerber
generation
V High Speed Simulation, Signal Integrity.
V EMI/EMC Analysis for High Current & Power Products
V Design & Developing Military Product & Applications.
V After the PCB is manufactured the BBT is done and Component's
assembling and soldering. Knowledge of various Packages like CSP,
Fine BGA etc.
V Procuring Component and Manufacturing materials like PCB or Cable
Assemblies or Mechanical Enclosures for Product, or some customize
Transformer, Inductors, and EMI/EMC Shields.
V CE & FCC Certification Process to be followed in Designing. EMI EMC
Certification for SAMEER, ERTL & etc.
V Environmental Stress Screening testing for the Avionics Applications
V Real time Implementation and Testing with Hardware & Software Tools.
Significant Projects:
V Currently working on the Designing of the Power Management Unit, used
in the Unmanned Arial Vehicle based on Xilinx MIL Grade Spartan6 FPGA.
In this system Total-ACE Complete MIL-STD-1553 Solution used for
communications. In this Standards to be Qualified DO178B & DO245 &
CEMILAC Certification
V Worked on the Defense Project having highly complex Mixed Signal
design using multiple Modules boards having Xilinx Spartan 6 FPGAs,
Analog Devices SHARC DSP & Microcontrollers. The guidance control
electronics for the maneuvering of device is achieved by aerodynamic
control, as the product is the Avionics lots of Physical Fundamentals
implemented in Electronics.
V Laser Guided Devices guidance control electronics
V Description: The complete guidance control electronics is divided into
four main units called the Actuator Control Unit (ACU), Flight Control
Unit (FCU), Gimbals Control Unit (GCU) and Warhead Control Unit (WCU).
V Actuator Control Unit is responsible for deflecting the control surfaces
(fins) of the vehicle as demanded by the flight control unit from time to
time. ACU controls the fins of the missile using four three-phase BLDC
Motors. The main processing units were Motor driver L6235, SHARC
ADSP21363 and SPARTAN6 FPGA XC6SLX4-2CSG225I
V Flight Control Unit is the on board computer of the flight vehicle which
receives the data from various sensors on-board and utilizes it for
stabilizing, controlling and guiding the missile towards target.
Stabilization and control are achieved by implementing the autopilot
algorithms, which controls the flight vehicle in pitch, yaw and roll
respectively.
The main processing units were inertial measurement unit (IMU) unit SHARC
ADSP21363 and SPARTAN6 FPGA XC6SLX4-2CSG225I
V GIMBAL Control Unit is used for searching, acquiring and tracking the
target using laser seeker optical module LSOM which is mounted on GIMBAL
and controlled by two two-phase BLDC motors or Limited Angle Torquers
(LAT). The main processing units were two dual channel
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