Engineer Design Project Experience Time C++ Engineering

GEETIKA BANSAL

***-******** *******,******* (Punjab)

+919*********)| *******.**********@*****.***

VLSI / FPGA Design Engineer / Electronics Engineer

VLSI Professional with Masters of Technology in area of VLSI Design.Trained in engineering communication technologies that impact all levels of organizations. Offers logical, forthright thinking and able to provide effective solutions to solve difficult problems. Capable of objective analysis and skilled at making quick decisions based on wisdom, experience, and judgment, and having excellent presentation skills. Possess positive attitude, leadership quality, and hands-on teamwork.

Areas of expertise include:

• VLSI/FPGA Design

• Simulation and Synthesis

• Digital/Analog Logic Design

SUMMARY:

• Proficient with coding RTL & Behavioural using Verilog and VHDL.

• Experience with Synthesis and Optimization of Verilog/VHDL Code.

• Experience with FPGA implementation with Xilinx.

• Familiar with Microprocessors and Microcontrollers.

• Worked on Mentor Graphics Simulator and Synthesis Tool.

• Familiar with different kind of VLSI Architectures.

• Strong Digital and Analog CMOS Fundamentals.

• Familiar with Synthesis and Timing Analysis.

• Valid GRE Scores and done professional courses in C++ and J2EE.

TECHNICAL SKILLS

• Hardware Description Language: VHDL and Verilog

• Design Tools: ModelSim, SPICE (T-SPICE)

• Languages: C, C++

• Microsoft: Windows NT/98/95, Windows Vista, Windows 7

• Linux: Redhat

• Simulators: ModelSim VHDL/Verilog Simulators

• Synthesizers: Xilinx Implementation Tools

• Schematic and Layout Tool: Tanner Tool 12.6 (S-Edit, L-Edit, T-Spice)

• Application: FPGA Design, PCB Design, and Digital and Analog circuit design.

EDUCATION

Masters of Technology – VLSI Design (2009-2011)

MITS University, Rajasthan ( CGPA - 8.29/10)

Bachelors of Technology- Electronics and Commuication (2005-2009)

RIMT-IET, Mandi Gobindgarh ( Aggregate- 80.66%)

PUBLICATION

Research Paper got selected in “International Conference on Next Generation Communication and Computing Systems (ICNGC2S-10)” and published in “IETAN Conference Proceedings 0123” organized by IETAN,2010 entitled “ Architecting VLSI Systems-A Review”.

ISBN No: 978-93-81068-00-7.

PROFESSIONAL EXPERIENCE and ACADEMIC PROJECTS

1. Thapar University, Patiala (Jan 2011- Present)

Position : VLSI Trainee (VLSI Department)

Thesis : Design and Implementation of 4-Stage High Performance 32-bit RISC Processor

Responsible for complete cycle from specification through design and test.

Developed the architecture.

Choose instruction set of 11 Instructions(NOP,ADD,SUB,AND,NOT,NOR,RD,WR,BR,BRZ and HLT)

Design and done RTL Coding in Verilog.

Wrote code for Instruction Fetch, Instruction Decode,Execution Unit and Memory Read/Write and Registers.

Implemented Hardware Detection logic inside architecture.

Provided Branch and Halt support to architecture.

Avoided Flushing of pipeline if branch instruction occurs.

Done the Functional Simulation using ModelSim.

Done the Functional Synthesis using Xilinx Project Navigator.

Undergoing Implementation.

2. Thapar University, Patiala (Aug 2010- Dec 2010)

Position : Trainee (VLSI Department)

Project Entitled: Design and Implementation of 32-bit ALU

Developed the ultra fined grained design(1-bit) which allowed to replicate and make bigger design possible and helps in reducing overall design time.

Realize shift operators at 1-bit ALU which can be extendable to N-bit ALU.

Developed 1-bit ALU with following operations (Full Adder, Full Subtractor, AND, OR, XOR, NAND, NOR, XNOR, Increment by 1, Decrement by 1, Shift Left 1, Shift Right 1, Shift Arithmetic Left 1, Shift Arithmethic Right 1, 1’s Compliment and Clear).

Developed 1-bit ALU design to replicate and make 32-bit ALU ( 1-bit-4bit-8bit-16bit-32-bit).

Wrote Code using Verilog.

Done the functional simulation using “ModelSim S6.4e” and functional Synthesis by Xilinx Project Navigator “Xilinx ise 8.2i”.

Implementation done on “FPGA SPARTAN 3E Kit” and finally did documentation.

3. Bharti Airtel Limited, Chandigarh (Jan 2009- June 2009)

Position : Trainee (Switching Department)

Project Entitled: Connectivity of Airtel Chandigarh with Hutch Mohali

Created link sets and trunk groups.

Created C7 Signalling links and nailed up connection and handled voice trunks.

Software used: NET M.

4. RIMT-IET, Mandi Gobindgarh (Sept 2009 - Dec 2009)

Position : Programmer and Circuit Designer

Project Entitled: Electronics Voting Machine using Microcontrollers

Designed Electronic Voting machine using Embedded C language.

Complier used is keil uVision3.

Microcontroller : ATMEL89C52, LCD: 16*2 Display and Communication Interface: MAX232.

5. NIIT, Patiala (Jun 2007 - July 2007)

Position : C++ Programmer

Project Entitled: Student Training Agenda using File handling (C++)

Designed to handle all records.

Programming done in C++ (used File handling)

Various Modules are : Add records, Display records, Search records, Check records, Update records, Delete record and Delete all records.

EXTRA ACTIVITIES AND TEACHING EXPERIENCE

1. TutorVista Private Limited, Bangalore (Jan 2010- Present)

Position : International Online Tutor (Part-Time)

Subject : Maths (Higher Grades)

Responsible for handling students of higher grades.

Teaching Maths to International students.

Conduct online sessions.

2. Etutorworld, Bangalore (Jan 2011- Present)

Position : International Online Tutor (Part-Time)

Subject: Maths ( All Grades)

Conducted online sessions.

Prepared students for Tests.

Prepared students for Olympiads and other exams online.

Conduct assessment tests from time to time.

3. MITS University, Rajasthan (Aug 2009 - June 2010)

Position : Lab Engineer (Teaching Assistantship)

Subjects: Digital Electronics, VLSI, Digital Communication

Conduct Labs of B.Tech students.

Labs Taken : Digital Electronics Lab, VLSI Lab, and Digital Communication Lab.

Helped students in completing their experiments.

4. Transwebtutors, Noida (Aug 2010- Jan 2011)

Position : International Online Tutor (Part-Time)

Subject: Electrical Engineering (VLSI), Computer Science (C++) and Maths

Taught Australian Students CMOS VLSI Digital Design.

Taught Dubai Students C/C++.

Conducted online session of students from all over world (for Maths-All Grades)

Prepared student assignments on time and provide them guidance.

5. Awarded with “Award of Honour” by RIMT Training and Placement Department.

6. Awarded with “ Certification of Merit” in “ Circuit Assembling” held at RIMT-IET for bagging third position.

7. Completed Professional courses in “C++ and J2EE” from NIIT, Patiala.

8. Industrial Visit at “C.E.E.R.I”, Pilani.

PERSONAL DETAILS

• Languages Known: English, Hindi, Punjabi

• Date of Birth: 24 Dec, 1987

• Sex: Female

• Nationality: Indian

• Marital Status: Single.

References: Available on request.

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