Design System

SATHISH KUMAR D Mobile: (0-953******* No.**,*nd Cross,4th Main, Email: *************.*@*****.***

Jayanagar 1st Block East,

Byransandra,

Bangalore - 560 011.

_______________________________________________________________________

Objective

Seeking a challenging position in Esteemed Organization where my skills and experience will greatly enhance the company's success and my personal growth.

Summary of Qualifications

C programming

Good exposure to technology by undergoing additional training in VLSI Design

Good knowledge of Digital Circuits

Experience in writing RTL models in Verilog HDL and

Testbenches in System Verilog

Good understanding of the FPGA and ASIC design flow

Awareness about the PSL scripting language

Experience in using industry standard EDA tools

Good working knowledge of Linux

Core Competencies

HDLs : Verilog and VHDL.

HVLs : System Verilog

EDA Tool : Xilinx ISE and Modelsim.

Verification

Methodologies : Constrained Random Coverage Driven Verification &

Functional Coverage

TB Methodology: VMM from Synopsys

Domain : Digital Design methodologies, ASIC/FPGA Design Flow.

Knowledge : RTL Coding, FSM based design, Simulation, Synthesis,

Code Coverage, Functional Coverage, Static Timing Analysis.

Professional Qualification

Education University/Board Institution Year of

Passing % of

Marks

B.E.(E.C.E) Anna University,

Chennai C.Abdul Hakeem College

Of Engg & Tech,

Vellore. 2011 75

X Std State Board Govt. Hr. Sec. School,

Vellore. 2005 82.6

XII Std State Board Don Bosco Hr. Sec. School,

Katpadi, Vellore.

2007 84.41

Maven Silicon Certified Advanced VLSI Design and Verification course

from Maven Silicon VLSI Design and Training Center, Bangalore Year: July - Dec 2011

VLSI Projects at Maven Silicon

Real Time Clock – RTL Design and Verification

HDL: Verilog, VHDL

HVL: System Verilog

EDA Tools: Xilinx ISE and Modelsim

Implemented the RTL Coding for the Real Time Clock using Verilog HDL and converted the implementation in VHDL

Performed functional verification for the RTL using both Verilog and VHDL.

Performed code coverage for the design using Modelsim.

Synthesized the design in Xilinx ISE.

Programmable Timer Interface – RTL Design and Verification

HDL: Verilog

EDA Tools: Xilinx ISE and Modelsim

Implemented the Programmable Timer Interface using Verilog HDL.

Performed functional verification for the RTL using Verilog HDL.

Performed code coverage for the design using Modelsim.

Synthesized the design in Xilinx ISE.

Dual Port RAM – Verification

HVL: System Verilog

EDA Tools: Modelsim, Questa – Verification Platform and ISE

Implemented the Dual Port Ram using Verilog HDL independently

Architected the class based verification environment using system Verilog

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

Stop Watch - RTL Design

HDL: Verilog

EDA Tools: Xilinx ISE

Implemented the Stop Watch using Verilog HDL.

Performed functional verification for the RTL using Verilog HDL.

Synthesized the design in Xilinx ISE

Traffic Signal Controller - RTL Design

HDL: Verilog

EDA Tools: Xilinx ISE

Implemented the Traffic Signal Controller using Verilog HDL.

Performed functional verification for the RTL using Verilog HDL.

Synthesized the design in Xilinx ISE

UART- IP Core – Verification

HVL: System Verilog

EDA Tools: Modelsim

Architected the class based verification environment using system Verilog

Verified the RTL module using System Verilog

Generated functional and code coverage for the RTL verification sign-off

Router 1x3 – RTL Design and Verification

HDL: Verilog

EDA Tools: Modelsim and ISE

Architected the design and described the functionality using Verilog HDL

Synthesized the design in Xilinx ISE

Performed Testbench verification for the RTL using Verilog

Performed code coverage for the design using Modelsim.

Engineering Project

Undergraduate Project

Title: An Inexpensive Extendable Framework for Embedded Smart Car Security

System

• This system prototype is built on the base of one embedded platform which is microcontrloller Atmel 8051, controls all the processes.

• From this we implement image-recognition techniques that can provide the important functions required by advanced intelligent car security, to avoid vehicle theft and portect the usage of unauthenticated users.

In Plant Training

BSNL (Bharat Sanchar Nigam Limited), Vellore.

ISRO (Indian Space Research Organization), Bangalore.

Extra-Curricular Activities

Type Writing English in Junior Grade level with Distinction.

Participated in National Service Scheme (NSS) Camp & First Aid Program

I did Multimedia presentation about Malnutrition in India in Sona College of Engg & Tech, Salem.

I donated My Blood to NIMHANS (National Institute of Mental Health & Neuro Sciences) Hospital, Bangalore.

Achievement

I got best performance awarded for Human Pyramid Stunt & March Past in My College Annual Sports Day Function.

Strengths

Self Confident & Self motivation

Hardworker

Good team player

Ready to learn new technologies

Personal Profile

Name : D.Sathish Kumar

Father’s name : D.Dhasarathan

Date of Birth : 4th Jan 1990

Age : 22 years

Gender : Male

Marital Status : Single

Nationality : Indian

Communication Proficiency : English, Tamil

Skills : Fast learner, Interpersonal skills

Hobbies : Reading & physical exercise

Experience : 6months

Address for comm. : No.25, 2nd Cross, 4th Main,

Byransandra, Jayanagar 1st Block East,

Bangalore - 560 011.

Permanent Address : No.9, Bakthavachalam Nagar,

Sathuvachari, Vellore – 632009.

Contact number : Mobile: (0-953*******, (0-962*******

Email ID : *************.*@*****.***

Declaration

I declare that the information and facts stated here in above are true and correct to the best of my knowledge and belief.

Date : 05.08.2012 D.Sathish Kumar

Place: Bangalore Signature

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