Staff IC Design Engineer / Program Manager

Vic M. Vadi

***, * **** ******, #***

San Jose, CA 95112-2432 *******@*****.***

Cell Phone: 408-***-**** Home Phone: 408-***-****

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SUMMARY: To seek a technical management position in a high growth company. Strong combination of both technical / circuit design expertise and communication, organizational and planning skills.

EDUCATION

12/03 – 12/05 MBA in Marketing Management. GPA: 3.93

University of Phoenix, San Jose campus, CA

GMAT: 790/800 Course work included E-marketing, Consumer Behavior,

Marketing Strategy, Operations Management, Finance, Accounting and Business Law.

Coursework included discussions on ERP, CRM, SCM and Internet Marketing. Analyzed several companies/industries in terms of competitive landscape, strategy, investment potential as well as best/worst business practices.

9/96 – 12/00 Master of Science in Electrical Engineering (Electronics)

Bachelor of Science in Physics & Electrical Engineering (DSP/Signal Processing)

Stanford University, Stanford, CA. Graduated with Distinction 6/2000, GPA 3.88. President’s Award for Academic Excellence. President’s Scholar. SAT-1600

RESEARCH AND WORK EXPERIENCE (US Green Card Holder)

3/01 – present Staff IC Design Engineer / Program Manager, Xilinx, San Jose, CA.

Over 30 Patent Applications filed (20 issued) on transceivers, high speed clock switching, clock architecture, dynamic reconfiguration, SRAM design and DSP.

 12/07-present Program Management, Serdes Technology Group

 Run systematic, focused IC design, verification and silicon validation/characterization meetings for 32nm and 40nm transceivers.

 Also run an Engineering Meeting to keep the designers in the Xilinx Asia Design Centers up to speed on the latest technical and program information.

 Lead the HSSIO (High Speed Serial IO) Solution team focused on Transceiver Solution with cross functional representation of Apps, protocol IP, SW, HW and test groups in order to plan / develop the full customer GT solution launch.

 PCS Design Lead for Spartan-6 GTP Transceiver.

 Ran PCS, overall schedules and verification meetings for two parallel 45/40nm transceivers for both the Spartan-6 GTP and Virtex-6 GTX products. Focused specifically on setting the top level tone for the PCS design, verification strategy and metrics, SW/HW deliverables for both 40nm products in parallel. The two PHY’s were designed to comply with leading serial standards such as PCIe Gen1 / Gen2, SATA, XAUI, SDI, CPRI etc. Drove focused meetings to resolve PCS and PCIe MAC interfacing issues to improve inter-group communication.

 Filled a variety of roles in a vital building year for the newly formed SERDES team and was promoted for my work. Gained expertise as GT project manager / PCS design lead under immense resource constraints and tight schedules.

 My strength in communication helped me with these complex projects involving verification contractors, outsourced IC design groups and remote sites.

 3/04 –12/07 IC Design, Advanced Products Group (Virtex series FPGA IC Design).

 Contributed to the Power Tiger Team charged with managing the low power solution across all of Xilinx’s product offerings. Developed methodologies for Block RAM (BRAM) power characterization for web power tool estimation.

 Managed the layout and layout schedule for a prototype Single Event Upset (SEU) tolerant FPGA targeted for Aerospace and Defense applications. Put together design checklists, MS Project schedules and other plans to meet tapeout date. Oversight of layout and drove full chip integration for the SIRF chip

 Ran the DSP and Block RAM Solutions Team, a cross functional group focused on integrating a customer focused solution bringing together silicon, software, soft IP Cores, and input from FAE’s/marketing. Contributed ideas and organized problem solving brainstorming sessions, while ensuring that the team met key milestones/metrics.

 Business Continuity Planning for Xilinx IC Design,

 Worked on new feature development for the Virtex-5 and Virtex-6 FPGA high performance DSP Block (Multiply-Accumulate). Cut clock to out by half by novel patented circuit topology and layout architecture for the DSP block.

 Maintained the timing speeds file, Usage Document and Application slides detailing the intended Customer use model based on the marketing requirements/strategy. IC Design-Software interactions for BRAM, DSP and CFG groups for the 65nm and 40nm generation.

 New Employee Training website for IC Design engineers. The 40nm website documents IC design flows, tool usage and general reference information for ASIC and custom design flows. This work included descriptions of full chip signals, guidelines for IC Design blocks to follow and a database to describe common mistakes of the past.

 Managed FPGA Configuration blocks layout schedule.

 3/02 – 3/04 Defined the Clock Tree Architecture and designed the CFG/Global logic (including design of the SRAM memory cell array) for the 90nm Virtex-4 FPGA. Interfaced and collaborated with multiple groups in pulling the chip together from the top level. Worked on many critical and challenging issues and achieved first silicon success on a very complex chip. I enjoy spending time on architectural, big picture issues as well as detail-level issues in mixed signal circuit design. Made heavy use of scripting and time management in order to implement a complex design and juggle a lot of responsibility under severe schedule pressure.

 Interfaced with Yield Engineering, Technology Development, Process Technology and other groups in order to increase the yield of the FPGA memory cells in the 90nm 300mm wafers manufactured by UMC and Toshiba.

 Several patents on high speed differential clocking

 3/01 – 3/02 Worked as a member of a team to design and verify an FPGA-embedded Multi Gigabit Transceiver for the 130nm Virtex 2 Pro chip. Dealt with many intricate aspects of the 3.125 GHz Transceiver design. I was also responsible for designing and implementing top level interface blocks and dedicated reference clocking paths. Our team won the Ross Freeman Award for Technical Excellence.

6/00 – 9/00 Summer Intern, Data Acquisition Group, Crystal Semiconductors, Cirrus Logic, Austin, TX. Designed, synthesized and tested a Low Power Digitally Tunable, Clock Multiplier.

6/97 – 9/97 Summer Intern, Advanced Product Research and Design Lab, Motorola, Austin, TX. Calibrated and qualified several metrology tools to measure copper wafers in a FAB.

7/95 – 10/95 Researcher, Particle Physics, Columbia University. I was a Westinghouse Science Talent Search Semifinalist. Received a monetary award from Mayor Rudy Giuliani and also won a gold medal from the NY Academy of Sciences for the same project.

SKILLS/INTEREST

 Tools: MS Project, Perl, Verilog, VHDL, Hspice, Opus, HSIM, Unix/Linux Shell commands, ModelSim, Nanosim, DC/Synopsys Design Analyzer etc. Familiar with Xilinx ISE. Experience with Digital, Analog, Mixed signal custom Circuit Design as well as ASIC flow.

 Strong teaching skills, written and verbal communication skills, effective in a team environment. Quickly learn complex topics and can explain them to others.

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