Project Data

CURRICULAM VITAE

AZRUDDIN ANSARI

S/o Fakhruddin Ansari

C/o Flat-401,Block-15

(Brilliance) SUNCITY,

Sarjapur Outer Ring Road,

Ibbalur, Bangalore-560102 Ph:097********

Karnataka. Email:*********@*****.***

Objective

To associate myself with a professional organization where in I can utilize my engineering and interpersonal skills by contributing effectively towards mutual growth.

Educational qualification

Class/Course Name of Institute Board/University Year of Passing Marks%

MS

(VLSI-CAD) Manipal Centre for Information Science Manipal university, Manipal 2012 7.56

(GPA)

BE

(Electronics and Communication)

Modi Institute of Technology, Kota

University of Rajasthan

2009

67.5

Projects

1. 2nd semester MS project

Project Name “An Embedded True Random Number Generator for FPGAs in VERILOG”

Language , Tool Verilog , VCS tool, Mentor’s Modelsim

Duration 3 Months

Description Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. Until recently, designers using FPGAs had less than optimal choices for a source of truly random bits. It produce random bits at speeds of up to 0.5 Mbits/second with good statistical characteristics.

Guidance Mr. P.K. Shetty(Prof, MCIS, Manipal)

2. 1st semester MS project

Project Name “Universal Asynchronous Reciever Transmitter”

Language , Tool Verilog , VCS tool

Duration 3 months

Description In the asynchronous transmission the data is not send at all times. When no data is send the line remains in the High state. When the data is to be transmitted then the Low start bit is sent before the data byte and the receiver detects that bit and accepts the data byte. At the end of the data a High stop bit is send which tells the receiver that the data byte is ending here. Stop bit is also used for checking the framing error that may be due to the detection of false start bit or some noise in the channel.

Guidance Mr. Sundaresan C.(Prof, MCIS, Manipal)

3. Final year engineering project

Project Name “Maglev Train”

Tool Visual Basic

Duration 1 year

Description The project based on the working principal of repulsion mechanism of magnets. The basic mechanism behind propulsion of the train is called Hall Effect, for this we have used hall sensors with an electromagnet. Two parallel tracks are made up by permanent magnets, same kind of magnets are used at the side end of the train (bottom). An electromagnet is used with a hall sensor in the centre bottom side of the train. Here I use Microcontroller 89C52.

Guide Mrs. Suricha Bakliwal(Asst. Prof, MIT,Kota)

Technical Skills

Tools: VCS, Design Compiler, Magic, Spice.

Languages: C, Data Structures, Verilog.

Operating Systems: LINUX.

Areas of field interest

Digital Design and Verification, Computer Aided Design, Automation.

Extra Curricular Activities

• Done a Mini project on “Traffic Light Controller” in MIT, Kota.

• Member of Editorial Board of College.

• Member of school Cricket team.

• Secure good position in Bhartiya Sanskriti Gyan Exam.

• Qualified the NASSCOM Assessment of Competence ( NAC ).

Seminar Delivered

• Gave seminar on Moletronics in MCIS.

• Gave seminar on Skinput Technology in MCIS.

• Gave seminar on Haptic Technology in MIT.

Hobbies

• Listening music.

• Reading religious books.

Personal profile

• Name : Azruddin Ansari

• Date of birth : 23-10-1985

• Languages Known : English, Hindi, Urdu.

• Nationality : Indian

Declaration

I hereby declare that all the information mentioned above is true to the best of my knowledge.

Place: Bangalore

Date: AZRUDDIN ANSARI

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