Design Engineer

Kartik Raiker Phone: (***) *** – ****

***, ****** **, # ****, *** Jose, CA – 95110 Email: ************@*****.***

Objective

Seeking a challenging full-time position in Hardware Design, Verification and Test

Education

Masters in Electrical Engineering (May 2010)

GPA – 3.48/4.0 [San Jose State University]

Specialization: Digital Design and Analog-Mixed Signal Design

Bachelors in Electronics Engineering (May 2006)

GPA – 3.62/4.0 [Marathwada Institute of Technology, India]

Technical Skills

Development Environment: MS Windows, UNIX

Languages: C, C++, Verilog HDL, PERL

VLSI Frontend Tools: ModelSim, VCS

VLSI Backend Tools: Cadence, Virtuoso, Spectre Spice, Synopsys Design Analyzer

PCB Design Tools: Familiar with OrCAD and Mentor Graphics PADs

Laboratory Equipments: Oscilloscope, Digital Multimeter, Function Generator, Logic Analyzer

Work Experience

Hardware Design Engineer – Intern at Network Sound, Inc. (June 10 - Present)

 Create schematics and layout for multi-layered PCB using PADs and generate CAM files

 Test the products for acceptable values of THD using oscilloscope, logic and audio analyzer

 Designed Audio patch-bays, ADAT and Data Converters depending upon customer requirements

 PCB rework and assembling components

 Currently working on Actel ProAsic 3 FPGA to modify the existing design

Lab/Tech Assistant at College of Business, San Jose State University (Jul 08 – May 10)

 Maintain the computer labs and help professors and students with the equipments

Engineering Intern, Sterlite Optical Technologies Ltd. India (Aug 05 – Apr 06)

 Analyzed the requirements and conducted market research for possible solutions for automation

 Developed RFID Time and Attendance System to replace the magnetic punch card readers

 The software was developed using Visual Basics 6.0 and MS Access

 Features supported: Access control, leave management, salary calculation and report generation

Projects

Frequency Synthesizer

Designed a phase-locked loop using switched-current technique (SI PLL). Optimized the circuit for cost and area by replacing the passive loop filter with an on-chip switched-current FIR filter. An operating frequency around 11 GHz was achieved.

Process: CMOS 45nm Tools: Cadence, Virtuoso and Spice simulation tool

Analog Mixed Signal Design: Digital to Analog Converter

Designed a 7-Bit Thermometer Coded DAC. Cells like 7:128 bits thermometer decoder, current reference and current steering switches were made. Clean LVS was achieved and parasitic effects were extracted.

Process: TSMC 0.25 Tools: Cadence, Virtuoso, Spice simulation tool

Dynamic CMOS: 24 Bit Multiplier using Booth Recoder

Design implemented in high-speed digital logic. An operating frequency of 4 GHz was achieved by multi-phase clocking. Individual cells like partial product, carry save adders, CLA were designed and laid out hierarchically. The design was verified for timing and operation and a DRC clean layout was made.

Process: IBM 0.13 Tools: Cadence, Virtuoso, Spice simulation tool

ASIC Design: Data Slicer

Designed a data slicer that took a pair of I and Q signals, 12-bits each, and mapped it to QAM 6-bit code. Internal blocks included one and two flag models of FIFOs for synchronization and a slicer for mapping the inputs to the QAM code.

Language: Verilog HDL Tools: ModelSim 6.3c and Synopsys Design Analyzer

Computer Architecture: Tomasulo’s Algorithm

Implemented Tomasulo’s Algorithm to eliminate Write After Read (WAR) and Write After Write (WAW) hazards and to avoid Read After Write (RAW) hazards in assembly language program execution. The architecture was based on register renaming scheme and out of order execution of instructions.

Language: Verilog HDL Tool: ModelSim 6.5a

Advanced Digital Design and Synthesis: 4 by 4 Keypad Scanner and Encoder

The scanner decoded the pressed key and encoded it into packed BCD. Different modules designed were code generator, FIFO, controller, decoder / encoder. The design was synthesized to optimize for area, power and timing.

Language: Verilog HDL Tools: ModelSim 6.3c and Synopsys Design Analyzer

Static CMOS: 8 – Bit Arithmetic and Logic Unit

An 8-bit ALU was designed using Kogge-Stone Adder Network and AOI 3333. Schematics and layout were made and verified for functionality and timing. An operating frequency of 400 MHz was achieved.

Process: AMI 06 Tools: Cadence, Spice simulation tool, NC Verilog

Electronics Design: Temperature Controlling using PC

Designed a Data Acquisition System (DAS) to monitor temperatures on eight input channels. Controlling signals were generated using PC. Circuit was designed and laid out on the PCB using EAGLE layout editor. Interfacing program was written in C.

Language: C Tools and Equipments: EAGLE PCB layout editor, CRO, DMM

Related Coursework

Design of CMOS Digital Integrated Circuits, High Speed Dynamic CMOS Design, ASIC CMOS Design and Testing, Design for Test (DFT), Digital System Design and Synthesis, Analog-Mixed Signal CMOS Design, Semiconductor Devices, Linear Integrated Circuits

 Ready for relocation

 Available to start immediately

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