Project Engineer
Resume:
MANOJ PANT
Mobile: +91-886******* E-Mail: *****.******@*****.***
Aspiring to pursue entry level assignments in the domain of Electronic & Communication Engineering with a growth oriented organisation of repute.
EXECUTIVE SUMMARY
B.Tech. (Electronics & Communication Engineering) from TULA’S INSTITUTE, DEHRADUN.
Acquired fair knowledge and understanding of subjects like VERILOG HDL, Linux Operating System, Digital Design, C Language.
Proficiency at grasping new technical concepts quickly & utilizing it in a productive manner.
Believe in continuous learning and an innovative approach.
Adaptable and a quick learner; possesses skills to work under pressure.
Hard working, communication & interpersonal skills.
ACADEMIC CREDENTIALS
2007-2011 B.Tech. (Electronics & Communication Engineering) from TULA’S INSTITUTE, DEHRADUN Secured 68% marks.
2006-2007 Intermediate (Uttarakhand Board) from Govt. Inter College Lohaghat(Champawat).
Secured 78.8% marks.
2003-2004 Matriculation (Uttarakhand Board) from V.H.S.V.M. Lohaghat(Champawat).
Secured 76.5% marks.
IT FORTE
Programming Languages : C Programming Language
Operating System : Window XP, Linux ( CentOS-5.2)
EDA Tools : ModelSim 6.6b, Icarus Verilog, GTK wave
HDLs : Verilog HDLs, VHDL(Overview )
WORK EXPERIANCE
Company : Incise Infotech Pvt. Ltd
Designation : Trainee Engineer (VLSI Training)
Period : From 5th sept 2011 to present
VERILOG PROJECTS
Project 1: DESIGNED A PROGRAMMABLE TIMER USING VERILOG
Tool Used : Icarus, GTK Wave, Modelsim
Operating System : Linux,Windows
Language Used : Verilog
Description:
In this project a programmable timer was designed using Verilog language. The programmable timer is an eight-bit timer that allows three different modes, a one-shot timer, a pulse generator, and a 50% duty cycle waveform generator.
My Contribution:
Coding of programmable timer is done in Verilog and the Testbench is consisting of seven blocks:
1)Testcase 2) Top 3) Clock 4) Reset 5) Chip enable 6) Write logic 7) Load logic
Working Project 2: DESIGNED A FIFO USING VERILOG
Tool Used : Icarus, GTK Wave, Modelsim
Operating System : Linux, Windows
Language Used : Verilog
Description:
In this project a FIFO was defined using verilog language. A FIFO is a circuit which gives output in the form of First In First Out i.e. the data which comes first at input is the first one that goes out.
My Contribution:
Coding of FIFO was done by using Verilog language and after that Test Bench coding was done in verilog and then inputs were given in the Test Bench and output was checked using the GTKWave and Modelsim.
ACADEMIC PROJECT UNDERTAKEN
Project Title : Microcontroller based “DIGITAL LOCK SYSTEM” using zigbee module.
Tools Used : Proteus, AVR.
Overview : The system is based on Tmega32L controller by ATMEL. The system proposes a
Central control system to lock and unlock the device based on the password entered
By the operator. The remote connection has been realized using Zigbee module.
SUMMER INTERNSHIP
Report Title : Study of Defence Communication Equipments.
Period : 4 weeks (June’09-July’09)
Organization : Bharat Electronics Limited (BEL), Kotdwara.
Overview : Done a four week industrial training in “Bharat Electronics Limited (BEL)” in production department where I learned about the equipment which BEL is producing for Indian army like radar, antenna, etc.
EXTRA CURRICULAR ACTIVITIES
Participated in state level Science Exhibition.
Led the college team in Table Tennis & Badminton.
Worked as a supporting member in an NGO.
Runner up for the Badminton Doubles in college tournaments.
Won several prizes in Quiz competitions in inter school level.
PERSONAL DOSSIER
Date of Birth : 24th OCT, 1989
Address : Katchhari Ward, tharadhunga, Lohaghat (Distt-Champawat), UTTARAKHAND.
Languages Known : Hindi & English
DECLARATION
I hereby declare that the above mentioned information is correct upto my knowledge and I bear the responsibility for the correctness of above mentioned particulars.
Date --/--/----
Place- Noida (MANOJ PANT)
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