Design Project

BRAHMAREDDY PUSAPATI

VIT UNIVERSITY,VELLORE, Mobile: +91-741*******

Email: xck5mu@r.postjobfree.com

OBJECTIVE

To seek entry level assignments in the domain of VLSI Design with a growth oriented organization of repute, carving out a carrier path for myself in the growth of the company.

OVERVIEW

Working as Technical Intern at Synopsys(India) Pvt.Ltd

Gained professional knowledge and understanding of industrial trends by Cadence VLSI Certification Program (CVCP) through Cadence and IIDVT.

M.Tech (VLSI Design) from Vellore Institute of Technology in 2010-2012.

Good knowledge in Verilog HDL and Static Timing Analysis (STA) and ASIC FLOW.

TECHNICAL SKILL SET

• HDL KNOWN : Verilog HDL

• SCRIPTING LANGUAGE : PERL, TCL.

• AREAS OF INTRESET : ASIC design, Digital & Low power IC design, Physical design.

TOOLS KNOWN

• Functional Verification Tool : Modelsim, NC-Sim (Cadence), VCS (Synopsys).

• Schematic Editor Tool : Design Architect (Mentor graphics).

• Synthesis Tool’s : RTL-Compiler (Cadence), Synplify (FPGA), XILINX ISE 10.2i.

• Back End Tool : SOC Encounter (Cadence).

• Layout Tool’s : IC Station (Mentor graphics), Virtuoso Layout editor (Cadence).

ACADEMIC PROFILE

Course Board/ University Year of Study Marks (%) Division

M.Tech (VLSI) VIT UNIVESITY 2012 9.05(CGPA) Distinction

B.Tech(ECE) J.N.T.U, Hyderabad (MGIT) 2010 71.46 Distinction

INTERMEDIATE Board of Intermediate, AP. 2005 92.7 Distinction

S.S.C Board of Secondary Education, AP. 2003 84.66 Distinction

VLSI TRAINING PROGRAMME

Cadence VLSI Certification Programme Through Cadence and VIT:

Duration : Six Months

Expertise : ASIC Design – RTL Coding , Verification & Physical Design

PROJECTS UNDERTAKEN DURING VLSI TRAINING (CVCP TRAINING)

Title : APB based BIST for testing embedded RAM

Tools Used : NC Verilog, RTL Compiler, Cadence SoC Encounter

Language Used : Verilog HDL

Overview : Advanced Peripheral Bus (APB) is an interface in Advanced Microcontroller Bus Architecture (AMBA) widely used as on-chip bus in System-on-chip (SoC) designs. BIST can be used to test logic and memories, but are commonly used to test RAMs. March11 test algorithm is used to test embedded RAM in SOC.

Title : Design and Implementation of Traffic Light controller

Tools Used : NC Verilog, RTL Compiler, Cadence SoC Encounter

Language Used : Verilog HDL

Overview : To design a Traffic Light Controller to generate a sequence of switching ON/OFF Red, Green & Amber lights in a particular sequence that can be used to control the traffic lights of a typical four roads junction in a fixed sequence.

ACADEMIC ACTIVITIES(M.Tech)

Published a Paper on “An Area efficient and low-power design for decimation filter using CSD representation” in the “International Journal of Advanced Engineering Sciences and Technologies(IJAEST)” Vol No. 6,Issue No. 1,

Page No.111-115.

Published a Paper on “Design of a high gain self-biased folded cascode op-amp” in the “International conference on Science, engineering and Technology” Conducted in VIT University.

ACADEMIC PROJECTS WORKED IN(B.Tech)

Title : A COMPACT AND EFFICIENT FPGA IMPLEMENTATION OF DES ALGORITHM

Tool : Xilinx ISE 9.2i

Overview : To implement Data Encryption Standard (DES) Algorithm, which is a block cipher that takes 64 bit plain text and uses a 64 bit key to produce 64 bit plain text. It is based on a symmetric-key algorithm that uses a 56-bit key.

The Project implemented in Hardware Description Language (HDL) and Simulation & Synthesis is performed on Xilinx ISE and the design has been targeted to Xilinx Spartan 3E FPGA device.

Title : SOLAR TRACKING SYSTEM

Tool : keil microvision

Overview : Main objective is to determine the position of sun and track it using solar photovoltaic panel. Our project provides a solution for determining the position of sun in relation to any point on the surface of planet. The methodology implemented includes two sensors in two directions to sense the direction of maximum intensity of light. The difference between the outputs of the sensors is given to the micro controller unit, which is used for tracking and generating power from sunlight. It will process the input voltage from the comparison circuit and control the direction in which the motor has to be rotated so that it will receive maximum intensity of light from the sun.

PROJECT WORK DONE IN SYNOPSYS:

Title : OPTIMAL FPGA IMPLEMENTATION OF VARIOUS FIR & FFT

STRUCTURES IN ALTERA STRATIXV DEVICES USING SYNPLIFY.

Tool : Synplify Premier & Pro, Quartus P&R.

Overview : This project covers most industry utilized DSP structures (FIR & FFT) and implementation involves efficient packing of resources in mapper stage. Objective of this project is propose RTL Modeling which gives better mapping w.r.to Area and Performance. Implementation involves Modeling RTLs for various FIR structures including Direct, Transpose, Symmetry, Systolic, and Decimation & Interpolation structures in each case with & without pipeline registers, also covering Hierarchy & Flat Modeling of RTLs. Implementation of FFT structures includes variation w.r.to no. of points, radix & Decimation in time & Decimation in frequency.

ACHIVEMENTS:

1. Secured rank 7511 in GATE-2010

2. Secured rank 2965 in AIEEE-2006

3. secured rank 1271 Eamcet entrance-2006

4. Maintained consistency in academic record from 10th in 1st 5 positions.

5. Organized our branch technical fest MICROCOSM-09 in our college (MGIT).

DECLARATION

I here by declare that the above furnished information is true to best of my knowledge.

Date : (P.BRAHMA REDDY)

Place:

Contact this candidate