Electrical Engineer Design

Kushal Dave

407-***-**** • *************@*****.***

OBJECTIVE: To achieve excellence, to be resourceful and to pursue a challenging career as an Electrical Engineer.

EDUCATION:

San Jose State University, CA M.S. degree in Electrical Engineering (MSEE) GPA: 3.52/4.0 Completed: 12/2009

VGECG, Gujarat University, India B.E. degree in Electrical Engineering (BEEE) GPA: 3.86/4.0 Completed: 06/2007

RELEVANT COURSEWORK:

Semiconductor devices Device Physics Microprocessor Interfacing

Digital system design & synthesis High Speed CMOS digital circuits ASIC CMOS design

Advanced computer architectures SoC Design & Verification with System Verilog CMOS analog mixed-signal design

SKILLS:

• Coding/Scripting : Verilog HDL, VHDL, System Verilog, C, C++, Assembly 8051, Perl Scripting

• Tools Familiarity: Synopsis VCS, Design Compiler, Primetime, Cadence Virtuoso, Encounter, Xilinx ISE,

Mentor Graphics ModelSIM, Altera Quartus, MATLAB 7.5b, Keil Compiler, OrCAD

• Operating System: Unix, Linux, Window XP/Vista

• Communication Skill: Excellent verbal, written & interpersonal skills, Innovative leader, Strong work ethic,

Ability to analyze and troubleshoot problems, multitask & meet deadlines

EXPERIENCE:

• Teaching Assistant Electrical Engineering Department, SJSU 01/2009 - 12/2009

- Helped professor set up the digital design lab handled lab on RTL level coding using Verilog HDL/VDHL language, place and route on Xilinx ISE and implemented the design on Xilinx Spartan3E board.

- Assisted students to understand design & simulation on CAD tool like Xilinx, ModelSIM, and Synopsys.

• Design and Verification Engineer Universal Micro System , India 09/2006 - 12/2007

- Designed, tested and verified digital circuits for Auto Dialer, Motor Speed and Slip Measurement, Weight Scale using micro-controller. Developed embedded software coding in C programming language for 8051 MCU.

- Hands-on experience in ASICs, DC/AC motors, relays, switch-mode power supply and RFID technology.

PROJECTS:

• 16-bit Microprocessor using Speculative Tomasulo Algorithm: (ModelSIM, Verilog HDL, Team Project)

- Modules: Re-order Buffer (ROB), Reservation Stations, Common Data Bus (CDB), Register banks, 1KB Memory

- Verified architecture with complex test vectors eliminated hazards & generated printable output in text file.

• Designed PCI Express Layer Protocol for Memory Write: (ModelSIM, Verilog HDL, Individual Project)

- Modules: Transaction Layer (RX & TX), Data Link Layer (RX & TX), Physical Layer (RX & TX), CRC, I/O Buffer

- Performed functional verification using Verilog test-batch and System Verilog Assertions.

• 2D FIR Graphics Filter: (Synopsys VCS, Design Complier, Cadence Encounter, Verilog HDL, Group Project)

- Modules: I/O FIFO, Dual port RAM, RGB to YUV & YUV to RGB conversion logic, 5 row X 7 column 2D FIR filter.

- Tested on self testing test bench & synthesis using Synopsys Design Complier with a clock freq of 150 MHz.

- Performed placement and route in Cadence Encounter & carried out Design Exchange Format (DEF) for Virtuoso.

• 32-bit Address Generator with Dynamic Logic at 2 GHz: (Technology: ASU 45nm 1.0 V, Tool: Cadence Virtuoso)

- Modules: Multiplier accumulator (MAC), 7-bit array multiplier, 32-bit Carry Look-ahead Adder (CLA), D flip-flop

- Design was implemented using 5-phase clocking and latency was 19-phase.

- Designed schematic & physical layout, performed DRC & LVS, analog extraction was made using Cadence.

• Developed, Integrated and Tested an 8-by-8 ATM Switch: (Synopsys VCS, System Verilog, Individual Project)

- Used System Verilog, created the ATM port interface, completed the port definitions for Interface module, Instantiated and completed the module & simulated it, analyzed results and wrote a detailed project report.

• The Analysis of Area-Delay and Power-Delay Tradeoffs in Addition Circuits: (Xilinx ISE, Synopsis Primetime, VHDL)

- Area-delay and Power-delay Tradeoff curves for 8-, 16-, 32-, and 64-bit Ripple carry & carry look-ahead adder were analyzed, verified by Toshiba & TSMC libraries and synthesized using scripting commands.

- Performed STA to check setup & hold time violation using Synopsys Primetime for optimized circuits.

REFERENCES: Available on request.

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