Digital Design Engineer

TANMAY SHAH

**** ***** ***** **, *******, NC-***06, USA 919-***-**** *********@*****.***

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OBJECTIVE

A Computer Engineering position in a talented and motivated team.

EDUCATION

M.S. in Computer Engineering (Aug. 2008 – May 2010) GPA 4.0/4.0

North Carolina State University, Raleigh NC.

B.Tech in Electronics and Communication (Aug. 2004 – May 2008) CPI 8.2/10.0

Nirma University, Ahmedabad, INDIA.

EXPERIENCE

Research Assistant at North Carolina State University (Aug. 2009)

• Implementing “Memory Compiler for Multiport SRAM and CAM” under the guidance of Dr. Rotenberg, Associate Professor. It is an automated tool that generates the accurate data of area, access time and energy consumption, generates the layout and checks for the DRC and LVS for the given input configuration.

• Debugging “Verilog Simulator” of the FabScalar toolset, which is a framework for designing customized superscalar processor.

Intern at eInfochips Inc. (http://www.einfochips.com), Ahmedabad, INDIA (Dec 07 - Apr 08).

• Designed the Low Power FPGA based Processor, 32-bit SuperH-2 RISC architecture, in Verilog-2000.

• Implemented the Verilog library to generate the Functional Coverage report.

PUBLICATIONS

N. Choudhary, S. Wadhavkar, T. Shah, S. Navada, H. Hashemi, and E. Rotenberg, “FabScalar”, Workshop on Architectural Research Prototyping (WARP), held in conjunction with ISCA-36, June 2009, Austin, TX.

TECHNICAL SKILLS

• Hardware Description Languages: System Verilog, Verilog, VHDL

• Tools: Synopsys Design Vision, Design Compiler, Cadence SoC Encounter, Virtuoso, NC-Verilog, NC-Sim, HSPICE, Mentor Graphics Calibre, Questasim, ModelSim, Simvision, CosmoScope, MATLAB, Xilinx ISE , Xpower

• FPGAs: Xilinx Vertex

• Simulator: Simplescalar

• Script Languages: SKILL, UNIX Shell, Perl

• Languages: C, C++, Assembly

• Parallel Programming: OpenMP, CUDA

• Competencies: Digital System Design, RTL Design, Computer Architecture, C and C++ programming, Scripting

PROJECTS

• Created test plan and developed patterns to verify the functionality of pipelined LC-3 microcontroller in standalone environment using Random Regression with System Verilog, Object Oriented Programming using C++.

• Implemented the RTL for “Speech Recognition” algorithm in Verilog, synthesized and post annotated power and timing estimation in Design Compiler, carried out placement and route in Cadence Encounter.

• Designed the 3-level 8-channel DWT analysis filter bank for XC4VSX25 and XC4VLX25 Xilinx FPGA.

• Implemented multi-port 16X3 bit SRAM in sub-45nm CMOS technology in Virtuoso Layout Editor, performed DRC and LVS checks and performed post-layout simulation in CosmosScope.

• Parallelized the “Merge Sort” and “Binary Search Tree” algorithms using “Global and Fine grained locking” approach to enhance the speedup.

• Implemented “Multicluster out-of-order superscalar processor” using Simplescalar simulator and analyzed the effect on power consumption by increasing the width and depth of the processor using “Fabscalar” toolset.

• Designed a simulator in C for an out-of-order superscalar processor based on Tomasulo’s algorithm that fetches, dispatches, and issues N instructions per cycle.

• Implemented a flexible cache and memory hierarchy simulator in C++ and used it to design memory hierarchy well suited to the SPEC-INT 2000 benchmarks, within fixed area and power budgets.

• Designed the simulator in C++ for dynamic branch predictor well suited to the SPEC-INT 95 benchmarks.

• Designed the “Maze solving robot, Micromouse” using ATMEGA-32 microcontroller.

COURSE WORK

• VLSI System Design, Digital ASIC Design, ASIC Verification, Computer Architecture

• Digital Signal Processing, DSP Architecture, Embedded System Design, Computer Network

• Advanced Microarchitecture, Architecture of Parallel Computers, Multi-core/Many-core Architecture and Programming

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