Customer Service Electrical

HYUNGSANG YUK

****, ******* ***** # ****

Plano, Texas,75093 Home: +1-469-***-****

*********@*****.*** Cell: +1-469-***-****

PROFESSIONAL PROFILE

Research Scientist, University of Texas at Dallas 03/2009 – 02/2012

Developed high performance sub-5 nm “top-down” silicon NW transistors, which have high peak hole mobility, current density and drive current as well as low drain leakage current due to significant positive quantum confinement and well organized fabrication process.This study can deliver high performance for potential impact on both CMOS scaling andemerging applications such as bio-sensing. The results were published in Nano Letters,March and November 2011.

Fabricated the world smallest SiGe NWs (4 10 nm) applicable to photonic sensor by using electron beam lithography (EBL) with hydrogen silses quioxane (HSQ) resist and

inductively coupled plasma (ICP) etching.

Researched on direct wafer bonding of GaN on sapphire and Si wafer for the application of High Electron Mobility Transistor (HEMT) devices or light emitting diode (LED) or solar cell in case of special purpose.

Team Leader & FA Engineer, LG Siltron, Korea 09/ 2005 – 01/2009

Developed high quality 300 mm silicon on insulator (SOI) wafers for the application of CPU of game console such as PlayStation 3, XBOX and Nintendo Wii. This research work was nominated for 2007 LG Grand Research & Development Award in LG group that

consists of 53 branch companies (estimated value was $ 10 million).

Developed the world highest quality 200 mm strained-SOI (SSOI) wafers with tensile strain that can offer higher performance than that of SOI, being able to replace the Si channel for high speed CMOS application(estimated value was $ 5million).

Served as a failure analysis (FA) engineer for technical customer service in Si wafer business. Physical and chemical analysis was used to verify customer’s complaints and solved many issues raised by main customers such as Samsung, hynix, TI, SAS, Soitec,TSMC, SMT, NEC, etc.

Received a LG first prize at LG Academy and earned 93 point that has been a record of LG whole group since the course started.

Research Associate, Imperial College London, U.K. 10/2002 – 07/2004

Performed an Engineering and Physical Sciences Research Council (EPSRC) project titled "SiGe HMOS micro-power phase". Mainly fabricated HMOS transistors in cleanroom and measured electrical properties of the quantum well transistors.

Developed a novel SiGe on insulator (SGOI) formed by Ge implantation into SOI and

subsequent O2gas annealing. This is the world first success of high quality SiGe synthesisby ion-implantation.

Researcher, Korea Testing Laboratory, Korea 07/1995 – 07/1999

Tested electrical & lighting appliance and their components for safety, quality and energy efficiency by National regulations and International standards. Served as a member of Korean Standards (KS) council designated by Korean government for making or revising KS.

Served as an assistant secretary in IEC System for Conformity testing and Certification of Electrotechnical Equipment and Components (IECEE) Council of republic of Korea. The Scheme was based on the principle of mutual recognition (reciprocal acceptance) by its members of test results for obtaining certification or approval at national level.

EDUCATION

Ph.D. and Diploma in Electrical and Electronic Engineering

Imperial College London, U.K.,

Received Overseas Research Student (ORS) Scholarship and British Chevening Scholarship.

Master and Bachelor degree in Electrical Engineering

Received the first grade award and scholarship.

SKILLS

Failure analysis on yield drops related to crystal defects, metal contamination, gettering, etc by physical & chemical analysis and six-sigma tools.

Ion implanter, SIMS, XRD, SEM, FIB, TEM, Raman and AFM characterization skills and

analysis

Nano device fabrication process and electrical characterization

AWARDS, FELLOWSHIPS & LEADERSHIP

Outstanding paper award, International Conference on advanced electromaterials, Jeju 2011.

LG first prize, LG Academy (earned 93 point, a record of LG group), Korea.2008

Director of Daegu & Kyungbuk division of the Korean Institute of Electrical and Electronic Material Engineering (KIEEME), Korea. 2007 - 2008

Nominated for 2007 LG Grand Research & Development Award in LG group. 2007

A SOI team leader, LG Siltron, Korea. 2006 - 2007

Representative of LG Siltron in Silicon Wafer Engineering & Defect Science Center (Siweds),U.S.A.. 2006 - 2007

Overseas Research Student (ORS) Scholarship for high-quality international students, Institute of Education of U.K. Government, U.K.. 2001 - 2004

British Chevening Scholarship, Foreign and Commonwealth Office of U.K. Government, U.K..2001 - 2002

Chungbuk fellowship for top freshman, Postgraduate School of Chungbuk National University,Korea. 1993 - 1994

Chungbuk fellowship for top freshman, Chungbuk National University, Korea. 1985 - 1992

Sergeant, Korean army service, Korea. 1986 – 1988

PUBLICATIONS

JOURNAL PAPER

Hyung-Sang Yuk, Krutarth Trivedi, Moon J Kim, Jin-Heon Oh, and Kee-Joe Lim, “ Hole Transport Characteristics of [100] Long Channel 1D Devices ” Journal of Applied Physics, submitted. 2012.

Hyung-Sang Yuk, Jin-Heon Oh and Kee-Joe Lim, “ SiGe synthesis by Ge ion implantation” Japanese Journal of Applied Physics, accepted. 2012.

J. H. Oh, H. S. Yuk, and K. J. Lim, “Design of a novel type ultrasonic motor for high torque generation”,J. Electroceram. July 10, 2012

Kyung Soo Yi, Krutarth Trivedi, Herman C. Floresca, Hyungsang Yuk, Walter Hu, Moon J. Kim,“ Room-temperature Quantum Confinement Effects in Transport Properties of Ultra-thin Si Nanowire Field Effect Transistors”, Nano Lett., 11 (12), pp 5465–5470, 2011

Krutarth Trivedi, Hyungsang Yuk, Carlo Floresca, Moon Kim and Walter Hu, "Quantum Confinement Induced Performance Enhancement in Sub-5-nm Lithographic Si Nanowire Transistors ", Nano Lett., 11(4), pp 1412–1417, 2011.

Jin-Heon Oh, Hyung-Sang Yuk, Cheol-Hyeon Park, Kee-Joe Lim, Dae-Hee Park and Hyun-Hoo Kim "An Analysis of the Resonance Characteristics of a Traveling Wave Type Ultrasonic Motor by Applying a Normal Force and Input Voltage", Ferroelectrics, 135-143, Volume 378, 2009.

J. H. Oh, D.W. Shin, H. S. Yuk, C. H. Park, H. H. Kim, B. H. Ryu, and K. J. Lim "Design of a Piezoelectric Pump Using No Physically Moving Components", Ferroelectrics, 144-151, Volume 378,2009.

Ji-Young Kim, Jaeyeop Lee, Won-Wook Park, Jae-Young Leem, Hyukhyun Ryu, Won-Jae Lee, Ying-Ying Zhang, Soon-Yen Jung, Hi Deok Lee, In-Kyum Kim, Suk-Jun Kang, Hyung-Sang Yuk, Keumwoo Lee, Sunyeol Jeon and Hyeongtag Jeon, "Effects of strained Silicon Layer on Nickel Germano Silicidefor Nano-Scale CMOS Device", Japanese Journal of Applied Physics, Vol. 47, No 10, 2008.

Ji-Young Kim, Jaeyeop Lee, Won-Wook Park, Jae-Young Leem, Hyukhyun Ryu, Won-Jae Lee, Ying-Ying Zhang, Soon-Yen Jung, Hi Deok Lee, In-Kyum Kim, Suk-Jun Kang, Hyung-Sang Yuk, Keumwoo Lee, Sunyeol Jeon and Hyeongtag Jeon, "Study of Nickel Silicide Thermal Stability using SOI Substrate for Nano-Scale CMOS Device", Japanese Journal of Applied Physics, Vol. 47, No 10, 2008.

S. Kang, H. Yuk, I. Kim, J. Lee, J. Shim, B. Lee, J.G. Fiorenza, M. Curtin and A. Lochtefeld, "Strain degradation in strained-Si layers far thicker than the critical thickness grown on relaxed Si0.65 Ge0.35 layers", ECS Transactions Vol. 3, Issue 7, Pages 411-420, 2006.

CONFERENCE PAPER

Hyung-Sang Yuk, Krutarth Trivedi, Moon J Kim, Jin-Heon Oh, and Kee-Joe Lim, “ Si and SiGe Nanowire Transistors ” International Conference on advanced electromaterials (ICAE), Jeju, Korea,2011

Hyung-Sang Yuk, Jin-Heon Oh and Kee-Joe Lim, “ SiGe synthesis by Ge ion implantation” International Conference on advanced electromaterials (ICAE), Jeju, Korea, 2011

Hyungsang Yuk, Krutarth Trivedi, Carlo Floresca, Walter Hu and Moon Kim, " Quantum effects in Si nanowire PMOSFETs", ICPS, Seoul, Korea, 2010.

Krutarth Trivedi, Hyungsang Yuk, Carlo Floresca, Moon Kim and Walter Hu, " High Performance Lithographically Defined Back-Gated Si-nanowire MOSFETs with sub-5 nm Channel Width", EIPBN, Anchorage, Alaska, USA, 2010.

K. Trivedi, H. Yuk, C. Floresca, W. Hu and M. Kim, "High performance Si Nanowire P-MOSFETs" ECS Spring meeting, Vancouver, Canada, 2010.

C. Kim, J. Kim, X. Zhao, J. Leem, H. Ryu., W. Lee, S. Jung, H. Lee, I. Kim, S. Kang and H. Yuk, "The effects of strained silicon layer on Ni Germanosilicide for Nano-scale CMOS", NANOSMAT, Algarve, Portugal, 2007.

J. Kim, C. Kim, X. Zhao, J. Leem, H. Ryu, W. Lee, S. Jung, H. Lee, I. Kim, S. Kang and H. Yuk, " Study of Nickel Silicide Thermal Stability using SOI substrate for Nano-scale CMOS devices", ICMAT, Singapore, 2007.

Jung-Jin shim, Sang-Hyung Lee and Hyungsang Yuk, "Temperature and time dependent thermal splitting in plasma activated bonded wafer", ECS fall meeting, Washington DC, 2007.

S.H.Lee, J.C. Lee, I.K. Kim, S.J. Kang, J.J. Shim, J.S.Kim, B.Y. Lee and H.S. Yuk, "Fabrication of 300mm SOI for Nano CMOS Applications", Nano Korea, Seoul, Korea, 2006.

J.G. Fiorenza, P. kohli, S.J. Kang, M. Erdtmann, M. Curtin, S. Bengston, K. Matthews, B. Nguyen, I.K.Kim, H.S. Yuk, D.K. Lee, B.Y. Lee, A. Lochtefeld and R. Wise, "Systemic study of thick strained silicon NMOSFETs for digital applications", IEEE-ISTDM, Princeton, USA, 2006.

In-kyum Kim, Suk-june Kang, Hyung-sang Yuk, Dong-kun Lee and Bo-young Lee, “Formation of high quality strained-Si / strained-SiGe layer grown on the relaxed SiGe virtual substrate for Advanced CMOS application”, IEEE-ISTDM, Princeton, USA, 2006.

H.S. Yuk, K. Fobelets, T.J. Tate, D.J. Norris, X. Li, T. Zhang, M.P. Larsson, J. Zhang, L.F. Cohen and D.S. McPhail, "Formation of Novel SiGe-on- Insulator Substrate Structures by Ge+ Implantation and Oxidation for Strained-Si-MOSFETs technology", MRS spring meeting, San Francisco, USA, 2004.

H.S. Yuk, K.Fobelets and T. Tate, "Formation of Novel SiGe-on- Insulator Substrate Structures by Ge+ Implantation and O2 Gas Annealing", IEEE-5th ULIS, 23, IMEC, Belgium, 2004.

H.S. Yuk, T. Tate, K. Fobelets, J. Zhang, D.S. McPhail and R.J. Chater, "Fabrication Technique of SiGe-on-Insulator (SGOI) substrates by Ge+ Implantation for strained-Si SiGe Hetero-structure-CMOS technologies", IEEE-IMFED, Tech. Dig., 15, Osaka, Japan 2003.

Hyung-Sang Yuk, Tom Tate, Richard Chater, Sonia Li, Ryan Ferguson and Kristel Fobelets, "SiGe on insulator for micro-power devices", The Future of Electronic Devices, Institute of Physics, London, UK,2002.

S.H.Jeong, H.S.Yuk, K.J.Lim and S.G.Park, "Performance of screw-like piezoelectric actuator" Advanced Computational and Design Techniques in applied Electromagnetic Systems, Proceeding of ISEM, V6, pp. 341-344, 1994.

S.H.Jeong, Z.S.Lee, H.S.Yuk, K.J.Lim and H.G.Ryue, "Piezoelectric Actuator using Ultrasonic Travelling Wave of Screw Form", IEEE Dielectric and Electrical Insulation Society Proceeding of International Conference on Properties and Application of Dielectric Materials, V1, pp. 21-23 1994.

H.S.Yuk, S.H.Kang, K.J.Lim, S.G.Park and D.H.Park, "Recognition of Tree Growing using PD Signal Analysis in Low Density Polyethylene blended with Aniline", KIEEME, pp. 202-205,1994.

H.S.Yuk, S.H.Jeong, K.J.Lim and S.G. Park, "The Characteristics of Screw-shaped Piezoelectric Actuator", KIEEME, pp. 21-24,1994.

H.S.Yuk, S.Y.Shin, Z.S. Lee, S.H.Kang and K.J.Lim,"Preparation of Solid Type Aluminum Electrolytic Capacitor employing conducting polymer and its Characteristics", KIEE, V3, pp. 19-22, 1993.

S.H.Jeong, J.S.Lee, H.S.Yuk, H.I.Chae, K.J.Lim and H.D.Bai, "Force Factor of the Stator used for ring type ultrasonic motor", KIEE, V (B), pp. 1125-1129, 1993.

S.H.Jeong, S.Y.Sin, H.S.Yuk, K.J.Lim and H.D.Bai, "Characteristics of Ultrasonic motor using flexural vibration mode of an annular- form piezoelectric ceramic", KIEE, pp. 19-23, 1993.

PATENTS

In-Kyum Kim, Suk-June Kang and Hyung-Sang Yuk, "Manufacturing method for SSOI wafer", US patent Pub.#. US 2009003875A1(2009), European Patent App. # 08162465.2-2203, China patent Pub. #CN 101373710, 2009.

Sang-Hyun Lee, Kyoung-Hwan Song, Hyung-Sang Yuk, Jung-Jin Shim and Jang-Seop Kim,

"Apparatus and method for cleaving bonded substrates" Korea patent, Reg. # KR 10-0879760, 2009.

Suk-June Kang, Hyung-Sang Yuk, In-Kyum Kim, Jae-Chun Lee and Sang-Hyun Lee, "Method for Manufacturing Silicon-On-Insulator wafer Improved in Surface roughness using SiGe Sacrificial layer" Korea patent, Reg. # KR10-0880106, 2009.

Kyoung-Hwan Song, Sang-Hyun Lee, Hyung-Sang Yuk, Jung-Jin Shim and Jang-Seop Kim,

"Apparatus and method for irradiating laser beam" Korea patent, Reg. # KR 10-0872808, 2008.

Jae-Chun Lee, Hyung-Sang YuK, Sang-Hyun Lee and Suk-June Kang, "Method for thermal process of SOI wafer" Korea patent, Reg. # KR10-0857386, 2008.

In-Kyum Kim, Suk-June Kang and Hyung-Sang Yuk, "Manufacturing method for SSOI wafer",Korea patent, Reg. # KR 10-0873299, 2008.

In-Kyum Kim, Suk-June Kang and Hyung-Sang Yuk, "Method for manufacturing SOI wafer", Korea patent, Appl. # KR 10-200*-*******, 2008.

Hyung-Sang Yuk and In-Kyum Kim, "Semiconductor, method of fabricating the same and apparatus for fabricating the same", Korea patent, Reg. # KR100738458, 2007.

Hyung-Sang Yuk and Suk-June Kang, "Method of fabricating Germanium-On-Insulator substrate using a SOI substrate", Korea patent, Reg. # KR100738459, 2007.

In-Kyum Kim and Hyung-Sang Yuk, "Method and apparatus for evaluating bonded strength", Korea patent, Appl. # KR 10-200*-*******, 2007.

Kyoung-Hwan Song, Hyung-Sang Yuk, In-Kyum Kim and Jung-Jin Shim, "Method and apparatus for splitting bonded substrate" Korea patent, Appl. # KR 10-200*-*******, 2007.

Jang-Seop Kim, Hyung-Sang Yuk, Sang-Hyun Lee, Kyoung-Hwan Song and Jung-Jin Shim, “Electrical measurement equipment for measuring characteristic of SOI", Korea patent, Appl. # KR 10-200*-*******, 2007.

Suk-June Kang, In-Kyum Kim and Hyung-Sang Yuk,"Heat treatment method for improvement of surface roughness of SOI-wafer and apparatus for the same", Korea patent, Appl. # KR 10-200*-*******, 2007.

Jung-Jin Shim, Hyung-Sang Yuk, Sang-Hyun Lee and Kyoung-Hwan Song, "Method of fabricating SOI wafer" Korea patent, Appl. # KR 10-200*-*******, 2007.

Hyung-Sang Yuk and Jung-Jin Shim, "Manufacturing method for SOI wafer", Korea patent, Appl. # KR 10-200*-*******, 2007.

In-Kyum Kim, Suk-June Kang and Hyung-Sang Yuk, "Method for fabricating Strained-Silicon-On-Insulator Substrate in which seed layer removed by dry etch", Korea patent, Appl. # KR10-2006-0128719, 2006.

Jang-Seop Kim, In-Kyum Kim, Suk-June Kang and Hyung-Sang Yuk, "SiGe-On-Insulator wafer using epitaxial alumina insulator and fabrication method thereof", Korea patent, Appl. # KR10-2006-0137065,2006.

In-Kyum Kim, Suk-June Kang and Hyung-Sang Yuk, "Method for growing silicon single crystal on Insulator and manufacturing method of Silicon on Insulator", Korea patent, Appl. # KR10-2006-0138421,2006.

Suk-June Kang, In-Kyum Kim and Hyung-Sang Yuk, " Method of controlling wafer warpage by SiGe layer deposition and Wafer manufactured thereof ", Korea patent, Appl. # KR10-2006-0138756, 2006.

Contact this candidate