Design Engineer
Resume:
Vikram Vangapally
****, ********** *****, *** # **
Edwardsville, IL 62025
Phone: 618-***-****
Email:****************@*******.***
Professional Profile
o Challenging and Creative Design Engineer with significant experience in VHDL, Verilog, ModelSim, OrCAD, Microcontrollers, Microprocessors and Matlab.
o Hands on experience in creating schematics for RTL, schematic capture, floor planning, timing closure and verification, place-and-route.
o Proficient at electronic semiconductor testing, Computer Aided Design tools (CAD) for device and circuit level simulations, Integrated Circuit Design.
o Strong knowledge of Ethernet protocols.
o Proficient at handling Layout design and testing of Integrated Circuits.
o Results-driven achiever, effective team leader and highly motivated individual with exceptional interpersonal skills.
Education
o Masters in Electrical and Computer Engineering
Southern Illinois University Edwardsville, IL, December 2010
G.P.A: 4.0/4.0
o Bachelors in Electronics and Communication Engineering
Jawaharlal Nehru Technological University, Andhra Pradesh, India, May 2008
G.P.A: 3.75/4.0
Technical Skills
Hardware Languages : Verilog HDL, VHDL, VerilogA, Verilog AMS, System Verilog
Programming Languages : C, C++ and OOPs concept, VB.net, Matlab
Scripting Languages : Perl, Ocean, SKILL
Assembly Languages : 8085, 8086 Micro Processors, Microcontroller 8051
CAD Tools : Cadence Schematic Editor – Composer, Layout editor – Virtuso, Placement and Routing tool – Encounter, Simulator – Spectre, Waveform Viewer – Simvision, Specman Elite, NC Verilog, ModelSim, Xilinx ISE WebPAC
Operating Systems : Windows, Linux, Macintosh, UNIX
Web Development Tools : Dream Weaver, Adobe Photoshop, Flash
Experience
IC Designer, SIUE Jan 2010 – Dec 2010
Worked on the design, simulation, layout of two IC’s namely HINP – 16C (Heavy Ion Nuclear Processor – 16 Channel) and PSD – 8C (Pulse Shape Discriminator – 8 Channel).
Circuit Designer, SIUE Jan 2009 - April 2010
Proctored examinations, maintained and monitored laboratory for student use, graded laboratory assignments as required, collect, collate, and distributed materials.
Heavy Ion Nuclear Processor designer Jan 2010 – Dec 2010
o Worked on Heavy Ion Nuclear Processor – 16 Channel (HINP-16C) used in radioactive experiments for detecting the energy of the radiating particle (using AMI 0.5µm process technology).
o Responsible for design, layout, simulation and testing.
o Optimized in terms of area, power, cost and noise.
o Tested at all process corners and operating voltages.
Brain Controlled Interface (BCI) Jan 2010 – Dec 2010
Presently working on the development of a custom, low power, battery operated single channel Application Specific Integrated Circuit (ASIC) that can be used in a BCI
o It is an implantable, battery operated ECoG – based BCI system.
o Device consolidates multiple analog integrated circuits(IC) into a single analog ASIC to be paired with the digital circuitry for signal processing.
o Includes Delta Sigma Analog-Digital Converter, Delta Sigma Digital-Analog converter, Anti-Aliasing Filter, Operational Transconductance amplifier designs.
Object Oriented Programmer Aug 2009 – Dec 2009
o Developed functional application specifications; systems design criteria and developing, testing and maintaining applications in accordance with specifications.
o Diagnosed and resolved defects in the code.
o Developed and documented functional and technical requirements.
Operational Transconductance Amplifier Designer Aug 2009 – Dec 2009
o Designed an OTA with a gain of 86.5612dB and a phase margin of 63 degrees in Cadence using CMOS AMI 0.5µm process technology.
o The OTA occupied an area of 0.0342 mm2 while consuming 75mW of power.
o Total noise at the OTA output in 1-3 KHz bandwidth range is 41.698µV, and the thermal noise was 0.64µV.
Band-gap Voltage Reference designer Aug 2009 – Dec 2009
o Designed a Band-gap Voltage Reference along with a pair of two PTAT current sink outputs in Cadence using CMOS AMI 0.5µm process technology
o When simulated at typical process corners the band-gap output voltage was 1.2025 Volts and the current sink outputs were 1 µA and 10 µA.
o The circuit is occupied an area of 0.303 mm2 while consuming 957 µW.
Class F Power Amplifier designer Jan 2009 – May 2009
o Designed a Class F Power Amplifier in Cadence using CMOS AMI 0.5µm process technology
o Optimized the OTA in terms of area and power.
o Tested for all process corners and operating voltages.
8-bit Arithmetic Multiplier designer Aug 2008 – Dec 2008
o Designed a 8-bit Arithmetic Multiplier in Cadence using CMOS TSMC 0.25µm process technology.
o Optimized the Arithmetic Multiplier in terms of area and power.
Designer Student Educational Processor (SEP) Aug 2008 – Dec 2008
o Designed SEP using a blend of structural, behavioral, dataflow styles of writing programs in Verilog.
o Simulated SEP using Cadence for error correction and finally synthesized using Xilinx Webpack.
Activities and Honors
o Presented a paper and poster at SORMA 2010 (Symposium on Radiation Measurements and Applications). The paper was titled “Multi –Channel Integrated Circuits for the Detection and Measurement of Ionizing Radiation”.
o Presented a paper at CAARI 2010 (International Conference on the Application of Accelerators in Research and Industry). The paper was titled “Multi –Channel Integrated Circuits for Use in Research with Radio Active Ion Beams”.
o Public Relations Officer (April 2009 - April 2010) for International Student Council (ISC) at SIUE.
o Active Member of Student Leadership Development Program (SLDP) at SIUE
o BotBall Table Judge for BotBall International Robotics Tournament held at SIUE during July 2010.
o Recipient of Academic scholarship from Tecumseh India Private Ltd.
o Best Student Award as an Under-Graduate for the year June 2005 – May 2006.
Course Work
Mixed Signal System Design and Modeling, Radio Frequency IC Design, VLSI/CAD Design, Advanced Digital System’s Engineering, Analog Integrated Circuit Design, Digital Image Analysis and Processing I, Digital Image Analysis and Processing II, Advanced Stochastic Process, System Modeling and Optimization, Network Engineering, Advanced Network Engineering.
References
Dr. George Engel
Professor at Southern Illinois University Edwardsville
IC Design Research Laboratory
Southern Illinois University Edwardsville, IL – 62026
Email: ******@****.***
Phone: 618-***-****
Website: http://www.ee.siue.edu/~gengel/
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