Project Objective
Resume:
OBJECTIVE
Seeking a challenging and enduring job in professional organization where my skills abilities could be fully utilized to achieve organizational goals and professional growth.
ACADEMIC EDUCATION
• B. Tech EEE from Newtons Institute Of Engineering, Macherla,(J.N.T.U.K),Guntur, A.P with 58.5%
• Inter mediate from Spoorthi Junior College, Sattenapalli, Guntur District, A.P with 80.6%
• SSC from Spoorthi High School, Sattenapalli, Guntur District, A.P with 75.4%
WORK EXPERIENCE
• Worked as a customer support representative in BRIGADE, Gachibowly, Hyderabad to the client Reliance communications from July-2010 to Dec-2010.
• Worked as a customer support representative in SHELL TRANSOURCE, Punjagutta, Hyderabad to the client SUN DIRECT (DTH) from Dec-2010 to Feb-2011.
• Worked as a Software Developer in KJ&GM Techno Solutions Pvt.Ltd, Miyapur Hyderabad from Feb-2011 to Aug-2011
PROFESSIONAL TRAINING
An Industry Oriented Trainee in VLSI PHYSICAL DESIGN from Institute of Silicon Systems Pvt Ltd., Hyderabad since August 2011 to till date
COURSE OUTLINE
VLSI Fundamentals, CMOS Basics, Digital Design Floor Planning, Power Planning, Placement and Routing, clock tree synthesis, static timing analysis timing optimization, cross talk analysis, IR Drop Analysis and Physical Verification.
TOOLS
Experience in physical design of 130nm and 90nm technologies using Cadence tool
• Cadence SOC Encounter –Floor Planning, Place & Route, and clock tree synthesis
• Encounter Timing System –Static Timing Analysis and Crosstalk Analysis
• RTL Compiler- Logic Synthesis
• Assura – Physical Verification
SOFTWARE EXPOSURE
Operating system : Windows, Linux, Unix
Languages : C, PHP, HTML
Scripting Languages : TCL (Basics)
PROJECTS
Project1
Objective : Timing Driven Layout
Tools : SOC Encounter, ETS.
Gate count/Area : 1, 64,364/838820.2 um^2
Macros /STD Cells : 12/31835
No. of Clocks : 7
Frequency : 150MHz
Technology/Layers : TSMC 0.13 micron/5 Metal Layers
Role: Performing sanity check, Design import , Floor Plan , Power Plan , Placement , Trail Route, Power Analysis, RC Extract, Timing Analysis, IPO, CTS, Adding filler cells, Timing Analysis.
Project2
Tools : SOC Encounter, ETS.
Gate count : 52,426
No. of Clocks : 3
Frequency : 333 MHz
Technology : UMC 0.18 micron
Role: Performing sanity check , Design import , Floor Plan , Power Plan , Placement , Trail Route , Power Analysis, RC Extract , Timing analysis , IPO , CTS , Adding Filler Cells , Timing analysis.
Project3(Block level)
Objective : Timing Driven Layout
Tools : SOC Encounter, ETS.
Gate count/Area : 1,70,736/ 1282334.9 um^2
Macros /STD Cells : 12/28703
No. of Clocks : 17
Frequency : 200MHz
Technology/Layers : TSMC 0.13 micron/5 Metal Layers
Project4
Objective : Logic Synthesis,
Tools : RTL compiler,
No. of Clocks : 2
Frequency : 200MHz
Technology/Layers : TSMC 0.13 micron/5 Metal Layers
Project5
Objective : Layout
Tools : Virtuoso
Layout : Basic CMOS gates.
B-TECH PROJECT
Project Name: Design And Simulation Of Static VAR Compensator Using MAT LAB Simulink
Abstract : This project will discuss and demonstrate how Static VAR Compensator (SVC) has successfully been applied to control transmission systems dynamic performance for system disturbance and effectively regulate system voltage.SVC is basically a shunt connected static VAR generator whose output is adjusted to exchange capacitive or inductive current so as to maintain or control specific power variable; typically, the control variable is the SVC bus voltage.
One of the major reasons for installing a SVC is to improve dynamic voltage control and thus increase system load ability.
Project Role: Designing & Coding.
MINI PROJECT
Project Name: PC TO PC COMMUNICATION USING RADIO FREQUENCY.
Field : MICRO CONTROLLER.
Duration : 1 month (Dec-09).
Team size : 4
Role : As a Team Leader, Coding and Designing
PERSONAL STRENGTHS
• Commitment, self motivating and analytical thinking
• Smart & hard working
• Accepting Challenges
• Ability to learn.
Contact this candidate