D/O Mr. Pawan Kumar Gupta
H.No.-284, Sector-8, Faridabad
Phone :- 090********
To work in a competitive and challenging work environment that fully utilizes my capability. Want to contribute to the best of my ability towards the growth and development of company and to pursue a challenging and srewarding career.
Total work experience of 1 year till date in the field of VLSI.
22nd June 2011 till date Working as a “Verification Engineer” in VLSI with HCL Technologies LTD., Noida
June2010 to Dec 2010 Worked as an “Academic Trainee” in VLSI with HCL Technologies LTD, Noida
Hardware Description Language: Verilog HDL, System Verilog HDL, VHDL
Languages: C, Network programming
Operating Systems: Windows, LINUX
Bus Architectures: AHB and AXI Bus protocol, SPI.
Aerospace protocols: ARINC 429 & ARINC 604 protocol
Verification plans and Testcases Development & Simulation for Functional Verification.
Tools Known : Simulation – Synopsys VCS, Cadence NCSIM, Mentor Modelsim
Debugging – Simvision, DVE
PROJECTS AND ROLES AT HCL:
1) Project Status - Complete
Name : Renesas ‘APE6 Scheduler Verification’ project
Based on : AXI protocol
Description : Functional verification of APE6 Scheduler block in System Verilog HDL.
Scheduler consists of 1 master and 2 slaves. There is a 32-bit address bus, 128-bit write
data bus and 128-bit read data bus . Scheduler schedules a request from the master using
My Role :
• Understanding the specifications and features of the block.
• Coding Test Cases in System Verilog for functional verification.
• Simulation & Debugging of Test Cases using Synopsys VCS simulator.
• Regression runs.
• Generation of Code, Toggle & Functional Coverage.
2) Project Status – Incomplete (Currently working on)
Name: HS (Hamilton Sundstrand) project
Based on : SPI & ARINC 429 protocol
Description : It includes design and verification of an Aerospace PnB(Protection & Build In Test) block
in VHDL. PnB Block generates some labels on its own and receives some labels from
another BnD block and transmits them to DMC. SPI protocol is used to read the data
stored in external EEPROM.
My Role :
• Understanding the specifications and features of PnB block.
• Preparation of Test Plan and coding of Test Cases in VHDL.
• Simulation & Debugging of Test Cases using Cadence NCSIM & Mentor Modelsim.
• Modification of Test Bench for verification of SPI Block.
PROJECTS AT COLLEGE LEVEL :
Name: Line Following Robot
Based on: Microcontroller 8051
Description: This project includes sensing a black line and maneuvering the robot to stay on course, while constantly correcting wrong moves using feedback mechanism.
MINI PROJECT :
Name: Computer Controlled Radio Transmitter
Based on: Morse Code Software
Description: This project includes communication between two computers via radio. It makes use of Morse Code Encoder that converts the text entered into short and long pulses(dots and dashes) and decoder that converts the generated pulses back into the same text.
Placed at HCL Technologies Ltd through on-campus recruitment.
Won Consolation Prize in ‘Award of Excellence Test 2003’, conducted by the Aryabhatta Educational Society, Chandigarh
Obtained a participation Certificate in the ‘Mental Mathematics Challenge Competition’ held in the school in 2003.
Captain of College Girls Badminton team.
Actively participated in ‘Electronics Tech Fest’ held in 2008 at YMCA, Faridabad.
Awarded the scholarship of merit in school consecutively for 2 years (2005-2007).
Obtained ‘Merit Certificates’ from class 6th – 10th at school level
Adaptability & Reliability
EXAMINATION PASSED YEAR PASSED INSTITUTION/PLACE PERCENTAGE TOTAL MARKS
( till VIII sem) 2011 Y.M.C.A. Faridabad 8.43(CGPA)
CBSE(class 12th) 2007 Modern Vidya Niketan School, Faridabad 80.8
CBSE(class 10th) 2005 St.Anthony’s Secondary School, Faridabad 91.8
DOB : 10th Nov, 1989
o Learning new Trends & Techniques and increasing knowledge through various media.
o Painting, Dancing, and Playing Games.
(All the details given above are true to the best of my knowledge)
DATE : 15/08/12 RICHA GUPTA
PLACE: FARIDABAD (Signature)