analog IC / RF design engineer

DEEPSHIKHA BISWAS Phone: 213-***-****

Email: *******@***.***

*****************@*****.***

TECHNICAL SKILLS

TOOLS and softwares: : Cadence Virtuso Schemetic/Layout, VerilogXL, Assura, Calibre, SpectreRF, DRC, LVS, ERC, EMI-EMC, IronCAD, Allegro PCB Editor, Solidworks, MathCAD,ADS,AWR, HFSS, PADS, EDA tools, Hspice, LTspice, Spice3, Pspice, Magic,Eagle, ePD, Verilog Synthesis, IRSIM, Synopsis,PowerView, Modelsim MXE, Mentor QuickSim, MATLAB, LABVIEW, SIMULINK, solidworks, Alliance , KEIL,UMPS, XILINX FPGAs and CPLDs, EEPROM, PLA( eqntott, espresso, MPLA ), VxWorks, EAGLEWARE, PE/TE, JTAG DESIGN & DEBUGGING Agilent 8960, altera-xilinx-lattice tools, Rf signal integrity tools

EQUIPMENTS: Network Analyzer, signal generator, noise figure analyzer, VNAs,RF Power meter, Spectrum Analyzer, Oscilloscope, RF Vector Signal Analyzers, Protocol analyzers, Experience with IC LAYOUT AND RF LAYOUT

Processors : 8085,8086, 8051, LM3S101, PIC,TI DSPs (62x, 67x, 64x, 55x), ARM Processors(ARM9E, ARM11, Cortex )

PLATFORMS: MS Windows, MAC,UNIX, LINUX, Code Composer Studio

Languages / Softwares : Perl, C/C++/ embedded C, JAVA, Photoshop, VHDL, VERILOG, Assembly Language, MS OFFICE SUITE

WORK EXPERIENCE ( MSEE , 4 years experience) : Bharat Electronics Limited(06/12/2007 through 07/18/2008) – mixed signal IC design engineer (full-time)

Bharat Electronics Limited (05/16/2009 through 08/06/2009 ) – graduate technical intern (RF design)

IISc (01/06/2005-05/21/2007) – intern (ANALOG CIRCUIT DESIGN)

PROJECTS :

ANALOG / MIXED SIGNAL DESIGN:

• MIXED ANALOG-DIGITAL BROADBAND IC FOR INTERNET POWER-LINE DATA SYNCHRONOUS LINK: the project focuses on the improvement of data rate.

• EMBEDDING ADC ON DIGITAL TELECOM ASICS: noise and its effect on ADC analyzedand modeled.

• VIDEO DECODER PLATFORM: An IC was developed to capture video signal and decode the information in it. The SNR vs accuracy of decoding in analog ,digital video sources was measured.

• DESIGN OF 12-BIT PIPELINED ADC USING 0.18 um CMOS TECHNOLOGY : low-voltage low power fully differential operational amplifier was developed. A switched-capacitor gain amplifier was developed followed by the development of a 12-bit pipelined ADC stage. The last step was the development of the three MSB stages of the pipelined ADC.

• DELTA-SIGMA ADC DESIGN ( both discrete time and continuous time)

• FILTER DESIGN: IIR, FIR, ANALOG FILTERS (passive, active)

• VCO design, PLL and clock recovery loop design

• VOLTAGE REGULATOR DESIGN ( bandgap , LDO), DC-DC converters, battery charge controllers

• OTHER DESIGNS: Class AB, D line drivers, equalizers (including adaptive equalizers), amplifiers (class A,B, AB), buffers, comparators, timing circuits, data acquisition design, power supply design

RF DESIGN :

• LNA DESIGN: (0.18 um) supports 3G modulation schemes (eg: 16QAM) and data rates.

• ACTIVE PEAKING CELL: yields broadbanded, maximally flat magnitude compensation of driver transistor

• SC FILTER DESIGN, other SC circuit designs

• ANALOG AND DIGITAL VARIABLE GAIN AMPLIFIER DESIGN (BASEBAND, RF, IF)

• MIXER (passive, active, I /Q),

• FILTERS (baseband, IF, RF),

• OTHER DESIGNS: Xtal oscillators, couplers,dividers, switches, coaxial microstrip filters, duplexers, RF transceivers, bandgap circuits, microwave circuits, analog IQ modulators, antenna design

VLSI DESIGN: SRAM and DRAM design

COMPUTER ARCHITECTURE: CPU ARCHITECTURE and Instruction set design

PCB LAYOUT EXPERIENCE (digital, analog, RF), behavioral modeling (analog, digital circuits)

DIGITAL COMMUNICATIONS:

• Implementation ( HW / SW co-design) of end to end digital communication system (modulation formats: QPSK, BPSK, 16-QAM, ASK, FSK, OOFSK , COFDM, MSK, GMSK, SOQPSK)

• Implementation (HW / SW co-design) of rake receiver for DS-CDMA .

• Implementation of VITERBI ENCODER AND DECODER, HUFFMAN CODER, LZW AND QM CODERS

DSP PROJECTS

• Development and implementation (on TMS320) of segmentation algorithm for content based image retrieval

• Adaptive sub-band coding of speech signals (and implementation on TMS processors)

• Implementation of FIR and IIR filters on TMS processors

• Optical character recognition of Kannada text document

• Steganography: integration of JPEG 2000 lossy compression scheme and BPCS steganography

EDUCATION and AWARDS :

MSEE (dec 2009) University of Southern California, Los Angeles, CA GPA : 3.9/ 4

BS (electronics, 2007) M.S.RAMAIAH INSITUTE OF TECHNOLOGY GPA :80%

 Junior Mathematics Olympiad-23rd ;

 National Level Science Talent search Exam-54th;

 2nd national Level Science Olympiad-9th

ANALOG design experience ( along with VLSI and COMPUTER ARCHITECTURE)

1) high speed I/O design (SPI, I2C, USB, Ethernet, PCI/PCIe) : simulation and layout

2) High-speed digital interfaces experience (Multi-Gigabit SERDESes, CDRs, DDR2 memories (> 233Mhz).

3) Design and working knowledge of Very high speed ASICs, ARM based sub-systems. state machines ( combinatorial, sequential, synchronous,asynchronus). real time clocks.

4) Experience with embedded systems design, high speed CAN transceiver design, DDS, FDE, SAS/SATA, ST/MIPS/ARM CPU, MPEG/H.264 decode

MOBILE COMMUNICATION and RF DESIGN experience:

1) RF frequency converters, RF front ends, repeaters, transceivers, RF Systems, RF antenna and its controls, RSSI, RF planning, design and optimization (GSM, CDMA networks).

2) RF propagation and channel modeling, signal processing and its algorithms, embedded sowtware development (RT and nRT), power systems and management, switching and networking, packaging, manufacturing, reliability and QA, systems engineering

3) Cellular System Design , multi user detection, signal integrity and network analysis, frequency planning and traffic management in dual band network

4) Physical Layer Mobile Communications, experience with CDMA/WCDMA/GSM/EVDO/UMTS/WiMax/LTE/.

5) Design of two way radio systems (VHF, UHF), trunking radio systems, digital radio systems (APCO, TETRA & iDEN), Communications Control Centers, Signaling and Remote Control Systems, Wireless Mobile Data Systems, Wireless Broadband and Customized Computer Aided Dispatching Systems.

6) Resource allocation (channel assignment, call admission, etc.); Protocols for data-oriented networks;

7) Mobility management and hand-off; Wireless LAN, satellite systems, etc.

8) Practical experience with :

a) Noise, NF, P1dB, IP3, and IP2 , Antennas & propagation, microwave transmission through circuit elements and channels, Link Budgets, SNR, BER, data rates, data symbol encoding and decoding,

b) radio access technologies as WLAN, MANET, SENSORS, GPS

c) OS, JINI, UPnP, P2P, VoIP, IPTV, WPKI, WAP, grids, clouds, ubiquitous computing

d) ad hoc and mesh networking (focus on 802.11, 802.15 and 802.16 )

e) 2G, 3G, 4G devices and networks (design experience)

9) Knowledge of Quality standards such as ISO, CMM/CMMi; KPI improvement

10) Hands-on experience with Ericsson OSS. Knowledge of CNA and CHA. Knowledge of RNO (MRR, NCS, FAS) and traces (MTR, CTR).

Knowledge of Ericsson BSS features, Ericsson BSS RF parameters.

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