Design Assistant
Resume:
Bichen Chen
Brooklyn NY
***** *******@********.****.***
OBJECTIVE To pursue an Analog/RF position (Recent graduate)
PROFILE Excellent EE background, especially in analog front end and RF design. Have been involving into 2 university level researches for recent 2 academic years Work as Research assistant).
EDUCATION New York University 09/2010---05/2012
(Polytechnic Institute) (will graduate in May 2012)
MS . Electrical Engineering GPA: 3.88/4
Nanjing University of Technology(China) 09/2005--05/2009
BS. Electrical Engineering GPA: 3.72/4
WORKING
&
INTERNSHIP EXPERIENCE Cisco system
Signal Integrity Group Intern, San Jose, USA
June.2011-Sep.2011
Simulation, testing, measurement
Nanjing Corona Lab. Suman Electronic Co., Ltd. China
Chip testing and PCB layout Engineer(Paid job)
Jul.2009-Jul.2010
Mainly focusing on Cadence and Protel print circuit board layout
Major products chip function testing
To get involved into board design team for PC peripheral devices design
Nan Shan Bridge Electronics Group Co., Ltd. China
Internship
Jul.2006- Sep.2006
C/C++ programmer
RESEARCH EXPERIENCE
Polytechnic Institute of New York University Hardware Laboratory, New York City
Research assistant
Dec. 2010- May.2011
1. Get involved into chip multiprocessor(CMPs) project. The purpose of this research to explore the impact of high-speed NoC architectures in emerging multi-core CMP designs.
2. Work in low power consumption group and implemented on FPGA chips for verification
Polytechnic Institute of New York University Hardware Laboratory, New York City
Research assistant
June. 2011- May.2012
1. To design a novel architecture SAR ADC chip. Mainly focus on Mix-signal design
2. Have submitted " An ultra low power scheme in SAR ADC" to SoCC 2012
3. Have submitted layout to TSMC to tape-out
Polytechnic Institute of New York University, New York City
Course project
1. Use VHDL to implement an FPGA based architecture for complex rule matching with l inspection of multiple TCP connections (RTL level)
2. VLSI custom design for a 32 bits ALU with design flow of floorplanning, synthesis, place & route, layout verification, static timing analysis, formal/ layout verification ( Transistor level)
3. VLSI semi-custom design(VHDL and Cadence) for memory in CUP (Mix signal design)
4. Unity gain buffer design with reduced offset and gain error (Amplifier design)
COURSE WORK Advance radio frequency circuit
VLSI Introduction
VLSI system and Architecture (mix signal)
VLSI verification
Master Thesis 1 Amplifier Design
Advance EMC
Advance Computer Architecture design
Computer hardware design (RTL level)
Master Thesis 2
PROGRAMMING LANGUAGE
(*:advanced skill level)
Programming languages :
C/C++ language*, HSPICE*, Cadence SKILL scripting language*, Cadence Virtuoso*,Cadence GUI ,MultiSim* VHDL/Verilog*, System Verilog*,A-verilog, MATLAB*, 8051 Assembly language, Perl Altera and Xilinx families FPGA*
REFERENCE
Name: N.Sertac Artan
Title: Research adviser
Email: ******@****.***
Tel : 718-***-****
Name: Zhiqiang Qiu
Title: Hardware manage
Email: ****@*****.***
Tel : 510-***-****
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