Design Verification Engineer

Tushar Agarwal

**** ** ***** *** **** # **** Tel: 971-***-****

Hillsboro, OR-97124 Email: **************@*****.***

Summary • Versatile engineer with current focus in Verification Strategies and methods.

• Proficiency working with RTL Coding Simulation and debugging.

• Proficiency in working with Vera and Verilog.

• Lab experience in Board bring up and Board testing.

• Design and development of BFMs, Transactors and Checkers for Verification Environment.

• Good understanding of flow of verification with broad view of entire process.

• Successful in interfacing with broad range of people in all stages of product development.

• Detail-oriented with ability to work well independently and under strict deadlines.

• Highly motivated, result-oriented, team player with excellent interpersonal skills.

• Detail understanding of automation using perl script.

Experience

Focus Enhancments, Oregon March 2006 – Present

Design Verification Engineer

Environment: Vera, C, PLI, System Verilog Assertion, Perl, VCS, Debussy, DVE, ARM Processor, DPI

Ultra Wideband (UWB) is an exciting new technology that creates a world of opportunities for new wireless applications. Based on the WiMedia Alliance UWB standard and Certified Wireless USB specifications from the USB-IF, UWB offers higher data rates for digital media applications. This is achieved by transferring data from Mac to Phy and vice-versa. This data is sent in form of packets over air. The Mac is controlled using ARM processor.

• Responsible for developing verification Plan and implementing it with focus on reusability.

• Implemented both direct and random test, along with transactor and BFM based on object oriented techniques (OOP) and RVM methodology.

• Initiated and implemented system Verilog assertion to improve functional coverage.

• Assert gate level test and check the functionality.

• Implemented coverage based test to verify the functional and code coverage.

• Worked closely with logic design team on various block (GAB, SOC, MAC, PHY, SRAM, AHB-AMBA) over specifications definition, bug resolution and meeting maximum coverage goals.

• Created perl scripts to help automation of test. Proved successful coverage results with regression.

• Implemented VMM planner.

• Worked in Lab during Board bring up and Board testing.

Intel Corporation, Portland, Oregon April 2005 – March 2006

Validation Engineer

Environment: ATE, Oscilloscope

Worked in product development lab along with school. Worked on latest processor and chipset.

• Performed structural and functional test and Validation on microprocessor and chipsets.

• Did trouble shooting and verification of the product.

• Performed verification of the faulty chips with respect to different parameters.

• Assisted in trouble shooting of various test vectors and ran them on ATE.

• Did product Platform Validation on microprocessor.

• Made report on the given product.

Portland State University, Oregon Sept 2005 - March 2006

Research Assistant

Environment: Modelsim, Verilog, Xilinx ISE

The Adhoc network consisting of wireless sensors was designed to be able to communicate with other sensors and finally to the microprocessor.

• Designed and verified the architecture of Adhoc network consisting of wireless sensors and microprocessor.

• IIC bus was thoroughly studied and its various communication mode was understood, especially its dual clock operation was learned.

• Designed IIC Bus using Verilog.

• Performed functional test along with timing verification.

• The design was simulated using Modelsim and finally synthesized using Xilinx ISE.

TATA Institute of Fundamental Research, Mumbai, India May 2003 – Sept 2003

Design Engineer

Environment: Modelsim, VHDL, Xilinx ISE

This RISC Processor was designed as a part of major project, with simple instruction set to reduce the complexity and to support reusability.

• Designed a flexible microprocessor, which can be reused as per the changes in the research.

• Synthesized and implemented the design on CPLDA using JTAG.

• Assisted other engineers to understand the basic architecture of design.

• Gave presentation on entire design to the whole research group.

• The micro architecture and Instruction set of some processors like 8085 and 8086 was analyzed carefully. Designed micro architecture for the processor based on research and analysis result.

• The entire design was than implemented using VHDL language.

• The processor was designed to be adaptable to changes in future technologies keeping in mind reusability of code.

• Various FPGA and CPLDA were studied and than the design were synthesized with the help of Xilinx ISE on CPLDA using JTAG cable.

Dagger Forst Tools Ltd., Mumbai, India March 2003 – Sept 2003

Electrical Engineer

Environment: CNC Machines, C

Worked on CNC machine, programming and mathematical calculations were done.

• Problems in the machine were identified and were solved with collaboration of other departments.

• Routine checks of machines were performed.

• Made a report on the performance and issues related to trouble shooting after proper analysis.

Academic Projects Portland State University , Oregon Jan 2004 - June 2004

Environment: Modelsim, Verilog, Xilinx ISE, VHDL

Designed and verified bus controller unit for 3.2-GHz Intel Xeon microprocessor with dual-channel DDR266 SDRAM interface capable of providing up to 4.3GB/s memory bandwidth, 8X AGP interface that delivers up to 2.1 GB/s of graphics data, and 66 MHz PCI bus interface.

• The architecture of bus controller was designed studying the Intel Bus controller.

• The Bus Controller was implemented and verified using snooping logic and MESI cache coherence protocol.

• This bus controller was modeled and verified in VHDL using modelsim simulator.

• The resulting HDL description was synthesized for Xilinx FPGA.

Antech Technologies , Mumbai, India June 2002 – Aug 2003

Teaching Assistant

Environment: Modelsim, VHDL, Xilinx ISE

Classes were provided to assist students to develop there logic design skills and HDL language.

• Assisted students in solving designing problems, tuning problems and understanding the concepts of VHDL programming.

• Designed lab assignments for students.

Computer Skills Hardware Languages : Verilog, VHDL, assembly language, NTB-VERA, C, Perl, DC_TCL

: System Verilog Assertions

Operating Systems : Unix, Windows NT/2000/XP, Linux

EDA TOOLS : Mentor Model Sim, Xilinx ISE, VCS, Cadence Tools, Logic Analyzer,

Oscilloscope, VCS, Debussy Verdi, Synopsys VMM Planner, DVE,

Leonardo Spectrum

Education

Portland State University, Portland, Oregon

Masters of Science, Electrical & Computer Engineering Sep 2003 – Dec 2005

R.A.I.T, Mumbai, India

Bachelor of Engineering, Electrical Engineering June 1999- July2002

Related Coursework

ASIC Modeling & Simulation Digital Integrated Circuits

Formal Verification of Hardware and Software Microprocessor System Design

Advance Communication System Design Signals and System Computer Architecture

Presentations

Presented a paper and gave a seminar on VHDL Synthesis and Simulation at Computer Society of India, Mumbai Chapter.

Achievements

Won a technical Model presentation at undergraduate level.

Activities

Current member of IEEE.

Represented School in various technical competitions at undergraduate level in India at state level.

References

Available on Request.

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