design engineer

ANUP T. G.

A-***, Bharath Nagar, BEML Nagar, KGF-563115

Contact: +919*********, +91-815*******; E-mail: **********@*****.***

EDA TOOL DEVELOPER (R&D ENGINEER)

Seeking a challenging and rewarding opportunity to work with an organization of repute which recognizes my true potential & effectively utilizes my excellent analytical & technical skills.

EDUCATION & CREDENTIALS

• M. Tech. (VLSI Design & Embedded Systems), 2012

PES Institute of Technology, Bangalore (VTU, Belgaum); 61.83%

• Professional Development Program (VLSI Design), 2009

Sandeepani - School of VLSI Design, Bangalore (Xilinx)

• B. E. (Electronics and Communication), 2008

Dr T. Thimmaiah Institute of Technology, Oorgaum (VTU, Belgaum); 57.55%

• XII (PCMB), 2003

First Grade College, Oorgaum (Karnataka State Board); 67.66%

• X, 2001

Kendriya Vidyalaya, BEML Nagar, KGF (CBSE); 66.66%

SUMMARY OF SKILLS

Dedicated, hardworking and focused individual, determined to add value to the organization I work for, through my exceptional knowledge and learning ability.

Recently completed M.Tech. (VLSI Design & Embedded Systems), with a degree of B. E. (Electronics and Communication) & Professional Development Program in “VLSI Design”, reliable as a fully contributing, responsible and accountable member of task/project teams.

Possess sound analytical, quantitative research and problem-solving skills; Good concepts in Electrical/Electronics Engineering including VLSI and MOS transistor basics; exposure to some circuit level simulators.

Good digital design background including programming language like MatLAB and Hardware languages like Verilog or VHDL; Good analytical skill to solve circuit level issues.

A systematic, organized, hardworking and dedicated team player with an analytical bent of mind determined to be a part of a growth-oriented organization.

GATE Qualified 2009, 2010 & 2011.

SKILLS

VLSI design, as VLSI circuits, CMOS VLSI design, logic design, Verilog and MatLAB coding

TECHNICAL SKILLS

Operating Systems: Windows 7/XP & Linux

Languages: C, C++, MatLAB

Modeling Languages: Verilog, VHDL

Synthesizer Tools: Xilinx ISE 10.1

Simulation Tools: Modelsim 6.5,Matlab 7.11

Synthesis Kits: SPARTAN-3E & VIRTEX-4 FPGA

MAIN PROJECT:

Project Title: Development of VLSI-Floorplanning Based On Particle Swarm Optimization.

Language: MatLab

Team Size 1

Duration: 6 months (During Mtech)

Description: Very large-scale integrated floorplanning is NP-hard in combinatorial optimization problem. The proposed algorithm can achieve the optimal and reasonable solution for the hard IP modules placement and also can be applied to multi-objective problem in floorplanning.

Project Title: Parametric Neuro Security System Using ANN

Language: MatLab

Team Size 4

Duration: 6 months (During B.E.)

Description: Layered model is built using Artificial Neural Network & the parameters such as trial number, time and length while entering the pass word by the user. This model also provides facility to know about unauthentication done by intruders with the details of date, time, trial number and length of pass word entered.

MINI PROJECTS: (during VLSI Design training from Xilinx)

Language: Verilog; Tools used: Xilinx ISE 10.1.03(nt); Board used: Spartan 3 board-xc3s200-4ft256

Project Title: Display moving geometrical object on 640*480 VGA

Team Size 2

Description: The purpose of this project was to display moving geometrical object, while generating VSYNC and HSYNC signals for 640*480 signals. The color of the geometrical object changes accordance with the input switch (rgb).

Project Title: Voting Machine

Description: The purpose of this project was to count the number of times the vote has been casted to 3 parties and display the number of votes casted to each party on the 7segment display.

Project Title: Display Vertical Strips While Generating 640*480resolution

Team Size 2

Description: The purpose of this project was to display 8 colors (3 bit rgb) vertical strips, while generating VSYNC and HSYNC signals for 640*480 signals.

Project Title: 3 Bit Sequence Detector for serial Input

Description: The purpose of this project was to detect given 3 bit sequence from a serial input.

Project Title: 3 Bit Sequence Detector for 8 Bit Parallel Inputs

Description: The purpose of this project was to detect given 3 bit sequence in 8 bit parallel input.

Project Title: 2 bit calculator for 9 different operations

Description: The project was made with 2 bit, 2 inputs from switches, 4 bit select option from input switches. Output on LED display.

EXTRA CURRICULAR ACCOLOADES:

Holder of NCC ‘B’ Certificate, Grade ‘C’, Oorgaum, Karnataka [2003].

Received Rastrapati Award (Scouts), BEML Nagar, Karnataka [2002]

Date of Birth: 24th Nov. 1985

Languages: English, Tamil, Telgu, Hindi, Kannada & Marathi.

Hobbies: Reading Technical papers, solving Suduko, chess, swimming.

Passport No.: H6053589, valid upto 21/06/2019

References: Available on request

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