Software Engineer

ZUBIN KUMAR

****, ** **** ******, *-***, Stoneridge Apartments, Gainesville, FL-32608 ● **********@*****.*** ●352-***-****

OBJECTIVE:

•Seeking a full time position or internship in the industry that makes the best utilization of my education, skills and technical experience.

AREAS OF INTEREST:

•Reconfigurable Computing and FPGA prototyping, ASIC design, Digital System Design, Image Processing, VLSI, Embedded Systems, Computer Architecture and Parallelization, Hardware and Software Co-design.

EDUCATION:

•Graduate Studies: Masters of Science (MS) in Electrical and Computer Engineering from University of Florida, Florida, USA. (CGPA-3.3/4, Graduated-May 2010).

•Relevant Courses: Reconfigurable Computing, Embedded Systems, VLSI, Advance VLSI, Computer Architecture, Parallel Computer Architecture, Machine Intelligence, DSP.

•Received partial fee waiver as Achievement Award for good undergraduate record.

•Undergraduate Studies: Bachelor of Engineering (BE) in Electrical and Electronics Engineering from Manipal University, Karnataka, India. (CGPA-7.76/10, Graduated-May 2007).

GRADUATE RESEARCH PROJECTS:

•JPEG Decoder Architecture for FPGAs: Implementing a JPEG decoder on FPGA for converting JPEG images to BMP images. The decoder is being implemented for partial runtime reconfiguration on Virtex 4 FPGA boards. (UF, CHREC-F4 group, project in progress).

•2-D IDCT Core: Developed a fixed point DSP core for 2 dimensional IDCT computations, compatible with hardware architectures of various FPGA boards. (Part of JPEG Decoder Architecture, UF, CHREC-F4 group, spring ’10 project).

•JPEG Encoder Architecture for FPGAs: Implemented a JPEG encoder on FPGA for converting BMP images to JPEG images. The encoder was designed to have partial runtime reconfiguration on Virtex 4 FPGA boards. (UF, CHREC-F4 group, fall ’09 project).

•FPGA-USB Interface Drivers: Developed 8 bit and 32 bit drivers to interface Virtex 4 FPGA boards to USB port using FTDI-TTL-232R cable. The drivers can be used with several families of FPGA boards to send and receive data directly from the USB port. (UF, CHREC-F4 group, summer ’09 project).

GRADUATE COURSE PROJECTS:

•Bio-Signal Processor for RFID Chip: Designed a low power Bio-Signal Processor for RFID chips, capable of performing FFT and time domain operations on various physiological signals (like EEG, ECG etc.) and giving values like power spectrum density, heart rate etc. as output. Power profiling and layout generation for this VHDL intensive design was done using Synopsys and Encounter tools. Power reduction was achieved by selective clock gating and designing the layout of an 8x256 dual port custom SRAM using Cadence 5.1, in 250 nm technology. (Advance VLSI Project).

•4x1 SRAM Design: Designed a 4x1 edge triggered SRAM consisting of basic 6T SRAM cells. The SRAM design incorporated read/write capabilities, conditional clocking, precharge and sense amplifier circuits. The SRAM layout was made using Cadence 5.1, in 250 nm technology. (VLSI project).

•Parallelization of Character Recognition Algorithm: Carried out formulation, design, translation and execution of a parallel character recognition algorithm that used Eigen Space projections. Speedup, communication-computation ratios etc. were analyzed. Parallelization was implemented in MPI and UPC. Also developed the sequential character recognition algorithm in C for benchmark purposes. (Parallel Computer Architecture Project).

•Prewitt Edge Detection Algorithm for FPGAs: Designed a pipelined architecture for FPGAs to implement Prewitt Edge Detection algorithm. Synchronized the architecture with C code to run on a processor using Dimetalk. Alpha max - Beta min algorithm was used to improve speedup. (Reconfigurable Computing Project).

•32 bit MIPS Processor Emulation: Implemented a 32 bit, 5 stage, pipelined, MIPS processor architecture in C. Developed an assembler to convert assembly level instructions to binary. Instructions were simulated in C. Special cache optimization was also implemented to improve speedup. (Computer Architecture Project).

•Implementation of A* Search for Solving 8 Puzzle: Implemented the A* search algorithm to solve the 8 puzzle in LISP. IDA* algorithm was also implemented to solve the puzzle. (Machine Intelligence Project).

PROFESSIONAL EXPERIENCE:

•UF Center for High Performance Reconfigurable Computing (CHREC-F4 Group). (Present): Currently working with the CHREC F4 group on implementing the JPEG baseline codec on FPGAs for partial runtime reconfiguration.

•Responsible for other activities in the group such as training new volunteers, supervising and coordinating their work, delegating tasks etc.

•Software Engineer, Infosys Technologies Ltd., India. (June 2007-July 2008): Work involved interfacing the Finacle Treasury banking application with client banks and resolving functional and non-functional issues logged by them and other development centers.

•Internships. (summer and winter 2005): Underwent 2 month internship at National Thermal Power Corporation plant in India (Control and Automation Unit) and at Samsung India Electronics Pvt. Ltd., India (Refrigeration Plant). Internships involved studying various digital control systems used in the power generation, processing and manufacturing industries.

NOTABLE UNDERGRADUATE PROJECTS:

•Remote Control of Electrical Devices using Mobile Phones and Microcontrollers: Developed a system to control electrical devices by interfacing microcontrollers and mobile phones. The scheme enabled low cost remote control of electrical devices over extremely large distances. The system facilitated features like access code checking, access code change, on/off toggle of devices, operation indication beeps etc. (Embedded systems implementation, assembly level programming project).

•Illumination scheme case study: Studied the illumination scheme of the Central Computing facility at Manipal University, carried out simulations to make the scheme more efficient and developed digital systems to automate it. (Illumination technology, digital system design project).

UNDERGRADUATE PAPER PRESENTATIONS:

•Paper on Smart Homes and Building Automation presented at the Innovative Building Solutions-2006, a national presentation challenge at Schneider Electric, India (3rd prize). The paper was also accepted for an international conference on building performance and simulation held in China in 2007.

•Paper on Controlling Electrical Devices Using Mobile Phones Interfaced with Microcontrollers presented at the Advance Energy Conversion Technology-2007, a national conference held in Manipal University, India.

•Paper on Power Saving through Daylight Harvesting and Building Automation presented at Cognizance-2007, national technical festival of IIT Roorkee, India (2nd prize).

SKILLS:

•Programming Languages: C/C++, LISP, VHDL.

•Parallel Computing Languages: MPI, UPC.

•Assembly Level Programming: Programming for 8085, 8086 and 8051, Assembly for MIPS.

•HDL Softwares: Xilinx ISE 9.2, 10.1, 11.1, ModelSim, ISim, RivieraPro.

•VLSI Softwares: Cadence, Synopsys, Encounter.

•Other Softwares: Matlab, Keil µVision microcontroller/microprocessor emulator, CImg image processing library.

•Others: Basic knowledge of SQL, HTML and Java.

EXTRACURRICULAR ACTIVITIES:

•Theater activities: On-stage and back-stage work. Worked with Torn Curtains, a contemporary English theater group in India, as actor and assistant stage manager.

•Events organized: Event Head for 2 years for TechTatva, the national technical festival of Manipal University. Organized events for groups like IE (EE chapter), ISTE etc.

•Other interests: Avid go-karter and highly interested in motorsports. Manipal University karting champion in 2006, in an event organized by Overdrive car and bike magazine. Also enjoy cartooning, 3-D designing and modeling.

REFERENCES:

•Dr. Ann Gordon Ross, Assistant Professor and CHREC member, Dept. of Electrical and Computer Engineering, UF. Contact: ***@***.***.***, Phone: 352-***-****.

•Mr. Jason Degen, Technical Director, University of Florida Performing Arts - Phillips Centre for Performing Arts, UF. Contact: ******@**************.***.***, Phone: 352-***-****.

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