Design Engineer

Hitenkumar Shingala

***, * *** **. ***#*** E-mail: *******@*****.***

San Jose, CA, 95110 Phone: 408 -398-1382

OBJECTIVE

Seeking an Internship/Full time position in the field of Electrical Engineering.

SUMMARY

 Performed transistor level CMOS circuit design.

 Used P&R tool and have good knowledge of RTL to GDS flow.

 Academic experience in deep sub micron technology

 Knowledge of scripting language and industrial standard EDA tools.

 Working knowledge of custom and ASIC design flow.

 Worked on Verilog HDL code for logic design and verification.

 Excellent communication and presentation skills. Self motivated, team player and enjoy problem solving.

EDUCATION

 Master’s of Science in Electrical Engineering Expected-Dec’10

San Jose State University, San Jose, CA (GPA: 3.47)

 Bachelors of Engineering in Electronics & Communication June’07

Gujarat University, India (GPA: 3.76)

PROFESSIONAL EXPERIENCE

Design Engineer Intern, Sahajanand Laser Technology, INDIA Jan’07-June’07

 Worked as an intern on the designing of Graphical LCD and Line Driver with the resolution of 320*240. The hardware unit “Image Selection and Display using Graphical LCD” was developed with Microcontroller 89V51RD2, RS 232 and Graphical LCD.

 Key tasks were schematic design of architecture in OrCAD, Programming of various graphical images in keil Compiler, Testing of design hierarchy, Soldering on PCB and loading of programs into microcontroller

RELEVANT COURSEWORK

ASIC CMOS design, High Speed CMOS Circuits, Advanced Computer Architecture, Advance Digital System Design and Synthesis, Mixed Signal IC Design, Analog Integrated Circuit Design, Semiconductor Device Physics, Digital Design for DSP and Communications/FPGA.

SKILLS

 Architecture Cache memory, Virtual memory, Cache coherence, protocol,

Microprocessor, Chipset, PC architecture, x86 architecture, GPU,

IA-32 architecture

 Programming C, C++(Basic), Verilog, ,Perl, TCL, Shell Scripting, Assembly Language

 Design Tools Cadence (Virtuoso, Allegro), OrCAD, Multisim, Ultiboard,

Electronic Workbench, L-edit, Cadence Encounter

 Simulators Xilinx ISE, Modelsim, Silos, Synopsys VCS

 Synthesizers Xilinx ISE, Synopsys Design Analyzer

 Operating Systems Windows 95 / 98 / 2000 / XP / Vista, UNIX, Mac OS

 Instruments Logic Analyzer, Oscilloscope, Spectrum Analyzer, Signal Generator, Digital

Multimeter(DMM)

PROJECTS (ACADEMIC)

Verilog and Gate Level Synthesis Projects

 Design and analyzed a sequential shift add multiplication circuit using Ripple Carry Adder (RCA) and Carry Look ahead Adder (CLA) ((VCS, Synopsys synthesizer, Tech Lib (Toshiba)) Spring’ 09

 Developed RTL code for 8 bit RCA and 8 bit CLA and implemented in shift add multiplication method. The code was synthesized in TSMC library using Synopsys Design Analyzer.

 Control logic was developed using mealy state machine. Successfully achieved the positive slack for the design. Layout was generated by using Gate level net list which was generated by Synopsys Design Compiler given as input file to Cadence encounter place and route tool.

 Essential tasks were analysis of area and power calculation for both adders, analysis of Static Timing Analysis (STA) and optimization of power and area.

 Design of 4x4 MAC design for 2C fractional format (Verilog HDL, Xilinx ISE 10.1, Multiplier core) Fall’08

 Developed RTL code for MAC engine which takes two 4-bits 2C fractional number, multiply them, and provides output of 8 bit.MAC engine accumulates the product to the 4 bit register with saturation logic. Code was synthesized in TSMC library using Synopsys Design Analyzer.

 Developed a logic which takes care of signed number, rounding and saturation. Key tasks were coding for test plan, simulation and timing analysis.

 Design 4X4 signed array Divider for 2c Fractional format (Verilog HDL, Xilinx ISE 10.1, Modelsim) Fall’ 08

 Developed RTL code for an ASIC block of 4x4 signed array divide using Xilinx IP core. The saturation logic of 4 bit numbers was implemented in Xilinx IP with given test cases.

 Code was synthesized in TSMC library using Synopsys Design Analyzer. Key tasks were coding for test plan, simulation, timing analysis.

Circuit Design and Layout Projects

 High Speed 27 bit Adder using dynamic domino logic (45 nm technology, Floor planning ) Fall’ 08

 The Circuitry was designed in Cadence Designing tool using IBM 0.13µm technology at the operating frequency of 4GHz in a team of 3. The design was separated into various blocks of group propagate, group propagate, block propagate and block generate.

 Major duties were transistor sizing with dynsize software, timing analysis of each block, verification, DRC and LVS check, layout in Cadence Virtuoso.

 Design of SRAM (45 nm tech, Transistor level design, Team Project, Floor planning) Spring’09

 Design was implemented using 6T cell topology and single bank array. SRAM consists of single Read and Write port (Single port memory). Design spec: Memory size: 8 Kbits, Access Time: 1 ns, Supply: 1v.

 Design includes Row and Column decoder, SRAM cell array, Sense amplifier, Write- circuit, Pre-charge circuit. Sizing of row decoder was done by assuming 300 ff loads t output. Similarly SRAM cell sizing was done by assuming 160 ff loads on bit lines. Schematic, simulation and layout was done using Virtuoso with DRC/LVS clean.

 Design of Phase Locked Loop (PLL) in Mixed Signal Design Spring’09

 Implemented the design of PLL in Cadence designing tool using 45nm technology with center frequency of 1GHz in a team of 3. Developed schematics of Phase Frequency Detector (PFD), current starved Voltage Controlled Oscillator (VCO), filter and Divider.

 Essential duties were schematics, transistor sizing, Simulation, debugging, frequency analysis and locking time observation, LVS and DRC check, layout in Cadence Virtuoso and post extraction.

Master’s Project

 Design of Pipelined Analog to Digital Converter (ADC) with Calibration Circuit (Ongoing)

 Design of 8 bit 20 MSPS Pipelined ADC in Cadence designing tools using TSMC 0.18µm technology. Pipelined ADC includes Sample and Hold Circuit (S/H), Sub Flash ADC and sub DAC at transistor level. Calibration Circuit consists of Static RAM (SRAM), Reference DAC at transistor level.

 Key tasks are transistor sizing, Simulation, debugging, elimination of gain error and nonlinearity by measuring ADC specifications i.e. INL, DNL and SFDR, LVS and DRC check, layout in Cadence Virtuoso and post extraction.

Contact this candidate