analog design,digital design,asic design
Resume:
DEEPU MATHEW ALEX
Email: *************@*****.*** | Mob: 099******** | Ph: 048********
CAREER OBJECTIVE:
Seeking career opportunities to enrich my skills in VLSI Domain and Analog design in an organization of repute.
ACADEMIC PROFICIENCY:
Course Discipline/
Specialization School/college Board/
University Year of Passing %/ gpa
M.Tech VLSI Design VIT University,
Vellore VIT University
Vellore 2012
(May/June) 8.67 CGPA
B.Tech Electronics &
Communication
Engineering St. Joseph’s College of Engg. & Tech,Palai M G University 2010 79.78%
Plus Two Computer science + Maths Stream St.Ephrem’s Higher Secondary School, Mannanam Higher Secondary Board,Kerala 2006 91%
SSLC S.S.L.C K.E English Medium School,Mannanam Board of Public Examinations, Kerala 2004 92.5%
PROFESSIONAL SUMMARY
As an Intern in IO solutions in TR&D - Central CAD & Design Solutions.
ST MICROELECTRONICS PVT. LTD., Plot No – 1, Knowledge Park-III, Greater Noida–201308 (U.P) (SEPT’11 – APR’12)
SYNOPSIS
Skilled Team Member having ability to lead and motivate teams to maximize productivity.
Good communication, analytical and problem solving skills.
Dedicated and highly ambitious to achieve personal as well as organizational goals.
Learning agility and adaptable.
TECHNICAL ACHIEVMENTS
EDA TOOLS
Schematic Design: Mentor Graphics Design Architect,Cadence virtuoso schematic editor.
Simulation: Mentor Graphics ModelSim, Mentor Graphics Eldo Simulator,SPICE, IOSIM.
Synthesis: Cadence RTL Compiler, Xilinx ISE.
Scripting languages : PERL,linux,unix,shell scripting,tcl.
HDLs: Verilog.
FAVOURED AREAS:
Digital Design, IO Design.
Analog Design and ASIC Design.
VLSI Design and Physical Design.
Verilog.
PUBLICATIONS AND SEMINAR ATTENDED
About to publish a paper on AUTOMATION FOR STANDARD I/O SCHEMATIC GENERATION.
Presented a paper on HIGH SPEED AND LOW POWER LEVEL CONVERTER in the 2nd International conference on Science, Engineering and Technology.
Presented a paper on AN EFFICIENT WAY TO DESIGN HIGH RADIX MONTGOMERY MULTIPLIER IN RSA PROCESSOR in the 1st International conference on Science, Engineering and Technology.
Seminar on CAN BUS and CANopen Technology.
Attended MPOWER, a 4-day training on personality development conducted by VERTICAL EYE.
ACHIEVEMENTS:
POSITIONS HELD
Electronics and Communication Student Association (ECSA) representative.
ECSA president from 2009-10.
IEEE Club’s Coordinator from 2008-09.
Event coordinator committee member for ECE department fest, Infusion’09.
ORGANIZING SKILLS
Organized ‘GREEN DREAM’, a movement against global warming jointly organized by IEEE and IYCN.
Co-organized an IEEE NATIONAL DISTINGUSED LECTURE PROGRAM (NDLP) on Free and Open Source Software.
Co-organized Aspire’09 (The seventh annual student convention on ISTE).
Co-organized, Infusion’09 ECE department fest.
HONOURS AND AWARDS:
Won MERIT SCHOLARSHIP for best performance during the academic years 2010-2011& 2011-2012(M.Tech).
Won first prize in aptitude test conducted by CSEA of SJCET in 2007.
Won second prize in full-time computer awareness course conducted by MAHATMA GANDHI UNIVERSITY.
School topper in Higher Secondary Examination for computer science-98%
ACADEMIC PROJECTS:
Project #1:
Title: AUTOMATION FOR STANDARD I/O SCHEMATIC GENERATION (32nm)
EDA Tool: IOSIM, Cadence Virtuoso Schematic Editor, Mentor Graphics Eldo Simulator, Xelga and PERL.
Description: Project basically, describes the process through which the schematic of the I/O could be designed, by running the full script and also blocks of I/O are tuned with the help of script.
Project #2:
Title: AUTOMATION OF MULTIPLE DRIVER MULTIPLE PREDRIVER FOR I/O (32nm)
EDA Tool: IOSIM, Cadence Virtuoso Schematic Editor, Mentor Graphics Eldo Simulator, Xelga and PERL.
Description: Project is used for automating four driver four predriver I/O using PERL script.
Project #3:
Title: Design of a High Speed and Low Power Level Converter for Multi-VDD Systems.
EDA Tool: Mentor Graphics EDA Tool using TSMC 180nm Technology.
Description: A novel level converter is proposed with low power and high speed and implemented in 180nm using mentor graphics design architect.
Project #4:
Title: Design of an Elevator-service in the Library.
EDA Tool: Cadence RTL compiler, SoC encounter.
Description: This project aims at designing an Application Specific Integrated Circuit for a seven floor elevator. The coding is done using VerilogHDL. The entire flow of ASIC design was covered until post layout simulation
Project #5:
Title: Automation of HF Radar Transmitting system.
EDA Tool: LabVIEW.
Description: In this project we can control the transmitting system of the HF radar automatically rather than manually. The automation is done with the aid of software LabVIEW.
PERSONAL PROFILE:
Name : DEEPU MATHEW ALEX
Sex : Male
Date of Birth : 14-12-1988
Permanent Address : Koprapurayil[h], Kairali Nagar,
Athirampuzha P. O
Kottayam[dist.]
Kerala-68656
Contact No : +919*********
DECLARATION:
I hereby assure that the above furnished information are correct and true to the best of my knowledge.
BENGALURU DEEPU MATHEW ALEX
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