Asic Design and Verificaton Engineer - Fresher

RESUME

ARUNRAJ KANDASAMY

“Sri Sai P.G.” **/***/* 7th ‘C’ Cross,

Jakkasandra new Extension,

Bangalore 560034

Mobile:91-888*******

E-mail:*******.*.***@*****.***

Objective__________________________________________________________________________________________________

A Design and Verification Engineer position in an organization seeking committed and fast

learner with knowledge of Verilog, test benches & verification techniques, along with handson

experience on Cadence tools.

Summary ___________________________________________________________________________________________________

Exceptionally talented Engineer with Advanced Diploma in VLSI design and excellent academic record.

Committed to the highest levels of professionalism and excellent interpersonal skills. Demonstrated expertise in Verilog HDL and front-end Cadence based ASIC flow with industry standard project work. Seeking a challenging role in ASIC design.

Skills Summary ____________________________________________________________________________________________

* System Verilog

* Logic Design

* Finite State Machine

* Cadence Tool Suite

* RTL Complier

* NCVERILOG

* Verilog HDL

* Simvision

* AHB Protocal

Project Experience ________________________________________________________________________________________

Major Project – Advanced Diploma in VLSI Design

I2C CONTROLLER WITH APB LITE PROTOCOL

* Literature Survey to understand APB Protocal and I2C Protocal

* Prepared Detailed Design Document For APB Master Implenetation and I2C Implementation

* Verilog Coding and simulation using Cadence NCVERILOG tool

* Test bench implemented in Verilog

* Synthesis using RTL Complier on TSMC 45nm technology

Mini Projects – Advanced Diploma in VLSI Design

* 8-Bit Serial ALU Design

* Synchronous FIFO

* Traffic Light Controller Design

Major Project – B.Tech Electronics & Communication Engineering

COLOR IDENTIFICATION ROBOT WITH AUTOMATIC OBJECT SORTING SYSTEM FOR MATERIAL HANDLING IN INDUSTRIES

* Up gradation of existing technologies and bringing in user interactive and more people

friendly techniques are fast catching up.

* Especially in industries where there is a heavy shortage of workforce and to increase

production speed and reduce human error to a drastic level the automation is of dire

need.

* In industries such as pharmaceutical companies this product will be highly helpful and

sometimes life saving too.

Major Project – Diploma Electronics & Communication Engineering

REMOTE CONTROLLED REAL TIME CLOCK WITH DEVICE CONTROLLER

* In this project, the presented circuit is capable of selecting any one of the device

connected across 8051.

* We aim to design a model, which would provide immense help to reduce the complexity of

the manual operation.

* This system on the whole provides a very effective guidance to monitor using remote at

reduced cost and less complexity.

Education _________________________________________________________________________________________________

INDIAN INSTITUTE OF VLSI DESIGN & TRAINING –Bangalore, Karnataka

Advanced Diploma in VLSI Design & Technology, Feb 2012 Percentage: 78.2

Four Month Full Time Course in ASIC Design based on Cadence flow. Course work included 150

hours of theory and 200 hours of lab work including industry standard project work.

B.E in Electronics and Communication Engineering, May 2011 Percentage: 69

PALLAVAN COLLEGE OF ENGINEERING, ANNA UNIVERSITY,TAMILNADU

Diploma in Electronics and Communication Engineering, May 2008 Percentage: 78.6

PALLAVAN POLYTECHNIC COLLEGE , DOTE UNIVERSITY,TAMILNADU

Secondary School Leaving Certificate, May 2005 Percentage: 66.2

GOVERNMENT HIGHER SECONDARY SCHOOL, STATE BOARD, TAMILNAU

Achievements ______________________________________________________________________________________________

* Participated in ‘District level science exhibition’ held at “Government Boys Hr. Sec. School”, Cheyyar in

NOVEMBER 2004.

* Got second prize in ‘Kho- Kho’ match held at “Government higher secondary school”, Menallur, During

JANUARY 2004.

* Participated in ‘National Level Technical Symposium’ held at “Vel tech engineering college”, Avadi in

AUGUST 2010.

Personal Details __________________________________________________________________________________________

Date of birth : 28, JULY, 1990

Marital status : Single

Nationality : Indian

Father’s name : Mr.A.Kandasamy

Mother’s name : Mrs.K.Amutha

Languages known: English, Tamil

Strength : Leadership quality, Self confidence.

REFERENCES AVAILABLE ON REQUEST

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