Engineer Assistant

Vaibhav Chhaya

*********

DOB: Dec, **, **** Email:***************@*****.***

Address: ****/*, ****** *-*, Gandhinagar. 382007. (M)095********. (H)079********

Education

****-**

Dhirubhai Ambani Institute of Information and Communication Technology

Gandhinagar (Gujarat)

M.Tech, Information and Communication Technology (VLSI)

- CPI 8.19/10

2004-08 Government Engineering College Chandkheda,

Gandhinagar (Gujarat)

BE, Electronics And Communication Aggregate 64.32%

2003-04 St. Xavier’s, Gandhinagar (Gujarat)

12th science (GSHSEB)

- 78.62%

2001-02 St. Xavier’s, Gandhinagar (Gujarat)

10th (GSEB)

- 85.43%

Skills

Expertise Area VLSI subsystem Design, Analog circuit design

Programming

Language C, Verilog HDL, VHDL

Tools and

Technologies Cadence Virtuoso, Xilinx ISE, Lt Spice, Multisim, Modelsim, Logisim, Silos

Technical Electives Digital System Architecture.

Internship

Industrial

Training Worked as a trainee in Nokia Siemens Network in BSS department consists of BTS and BSC

Guided by Vashishth Patel(Group leader). jan,08-may,08

M.Tech Thesis Work

CMOS Current-based Mixed-Signal Architecture for Vector-Matrix Multiplication Guide: Prof. Mazad Zaveri (May,11 – May,12)

The thesis work comprises of implementation of Vector Matrix Multiplication of 64 4 dimension with digital interface and analog internal operation with Lt Spice and Cadence Virtuoso tools 180nm technology.

Project

Implementation of HT12E encoder on Xilinx Spartan 3E using Feb 2011

Verilog HDL.

4 bit Carry Look Ahead Adder with carry generate, carry kill, March 2011

carry propagate blocks using 180nm technology in Cadence

Virtuoso.

Application to encrypt data using Verilog HDL based on MicroBlaze April 2011 using Xilinx FPGA Spartan 3E kit.

Guide: Prof. Rahul Dubey

Team Size – Four

Positions of Responsibility

Worked as a Development Engineer in Product development Department (R&D) in Electrotherm (I) ltd.

Oct,08 – Oct,09

Worked as Teaching Assistant for the course “Digital Circuit

Design” under Prof. Mazad Zaveri during autumn semester. Jan,11 – May,11

Jan,12 - May,12

Worked as Teaching Assistant for the course “Calculus and Complex variable” under Prof. Samaresh Chatterji July 11 – Dec 11

Awards and Achievements

Scored 539 in GATE 2010.

1st place at state level In Basketball tournament 2000.

Winner in CONCOURS inter college Basketball tournament 2011.

Cleared a general knowledge exam conducted by USO of India.

Paper publication

A paper for this thesis work with a title “CMOS Current-based Mixed-Signal Architecture for Vector-Matrix Multiplication” is published at national conference on ‘Recent Advances in Communication, Control and Computing Technology’ organized by IEEE, publication Benison Education, ISBN no.: 978-81-88894-34-5, pp. 137-143, March, 2012 Surat.

Workshop attend

Attend NEI workshop on DESIGN OF CMOS ANALOG CIRCUIT June 11 to 22,2012 at DAIICT, Gandhinagar. http://nei.daiict.ac.in/

Interests and Hobbies

Playing Basketball, Wandering with friends.

Declaration: The above information is correct to the best of my knowledge.

-Vaibhav Chhaya

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