Hardware engineer

Fei Zou

*** * ***** ***, ******** Park, CA *****; Cell phone: 408-***-****; Email: *******@*****.***

OBJECTIVE

Seeking a technical position in the field of electrical engineering/hardware engineering.

HIGHLIGHTS OF QUALIFICATIONS

• 2 + years hands-on experience in digital hardware design and implementation using VHDL/Verilog.

• 2 + years hands-on experience in printed circuit board (PCB) design, testing, debugging and soldering.

• In-depth knowledge of developing FPGA/CPLD chips application using VHDL/Verilog.

• Familiar with oscilloscope and logic analyzers.

SKILLS

Operating Systems: Windows XP, MSDOS, X-Windows (Linux).

Languages: VHDL, Verilog, Assembly Language, MIPS, C/C++, UML, HTML, XML, SQL.

Software: Xilinx ISE, Active-HDL, Xilinx Foundation Design and Simulation, ModelSim, Matlab, Cadence, Pspice.

Microprocessor and Chips: FPGA, CPLD, XS40 board (Xilinx), CYC68013 (Cypress), 8051.

EDUCATION

Santa Clara University, Santa Clara, CA

Master of Science, Electrical Engineering (VLSI Design and Test) Sep. 2006-June 2008

University of California, Riverside, Riverside, CA

Bachelor of Science, Computer Engineering Sep. 2001-Dec. 2004

RELATED COURSEWORK

Embedded Systems and Real-time Design, Logic Analysis and Synthesis, Design for Testability, Modern Time Analysis, Semi-custom Design with Programmable Devices, High-Level Synthesis, Very Large Scale Integration (VLSI) Design, Signal Integrity in IC and PCB Systems, Digital Signal Processing, Computer Architecture.

PROJECTS

• Designed and implemented an 18-bit up/down counter utilizing a dual-port Block RAM in Xilinx’s Spartan-3 device with Verilog (Working environment: Xilinx ISE 9.2i in Windows).

• Designed and implemented a single-multiplier MAC FIR filter utilizing a dual-port Block RAM and DSP48 in Xilinx’s Virtex-4 device with Verilog (Working environment: Xilinx ISE 9.2i in Windows).

• Implemented a self-addressing FIFO utilizing a dual-port Block RAM in Xilinx’s Spartan-3/Virtex II device with Verilog (Working environment: Xilinx ISE 9.2i in Windows)

• Designed and implemented circuit simulation for a 4-bit carry-look-ahead full adder, and performed and verified the layout of the full adder using mentor graphics VLSI CAD tools in Linux.

• Designed and implemented circuit simulation for a 2x2 SRAM using mentor graphics VLSI CAD tools in Linux.

RELATED EXPERIENCE

Santa Clara University, Department of Electrical Engineering, Santa Clara, CA March 2008-Present

Grader

• Conducted lab sections with 20+ graduate students.

• Assisted professor to grade homework and exam.

- Modern Time Analysis, Spring 2008.

Power, Energy & Environmental Research (PEER) Center, Caltech, Covina, CA July 2004-Aug. 2006

Hardware Engineer

• Designed and implemented logic designing in Fast Linear CCD Camera (1st Version) project to utilize CPLD XC95144 device with VHDL. The logic is used to generate the clock divider for shutter time of the camera, and provides driving logics to the linear array sensor and interface between the MCU and the ADC chip.

• Designed and implemented logic designing in Fast Linear CCD Camera (2nd Version) project to utilize CPLD XC95288 device with VHDL. The logic is used to generate the multi clock divider for shutter time of the camera.

• Developed and Implemented peripheral circuit schematic and layout of function generator, which used to generate various waveforms (Triangle, Sawtooth, Pulse, Squarewave), using a monolithic voltage-controlled oscillator IC with PCB123.

• Performed test and data collection, and analyzed simulation results/waveforms to assist project manager in improving original prototype designs.

• Provided technical support for PCB designers to enable them to make more informed decisions.

CITIZENSHIP U.S. Citizen.

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