Electrical Engineer Design

Amit Banik

*** * **** ****** #***, Arlington, Texas-76013

817-***-****|****.*****@****.***.***

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SUMMARY

• Electrical Engineer with 2 years of research experience in Semiconductor Fabrication (diffusion, photolithography, etching, metal deposition, dielectric thin film deposition (PECVD & PVD) and Characterization of semiconductor devices.

• Graduate Research Assistantship and Graduate Teaching Assistantship at the University of Texas at Arlington.

• Strong theoretical and practical knowledge of Semiconductor Fabrication Process Steps, Semiconductor Device Physics and Device Characterization.

• Self-motivated individual worked on research related MOSFETs and Solar Cell with minimal guidance.

• Developed an innovative process to prepare Pyramidal Zinc Oxide Particle for Solar Cell Application.

• Strong technical communication skill, quick learner and diligent as proven by my past research and teaching experience.

• Basic Knowledge of Statistical Process Control (SPC) and Design of Experiment (DOE) and Gauge R&R(GR&R).

EDUCATION

MS Electrical Engineering, University of Texas, Arlington, TX (Aug 2007 - Dec 2009)

GPA: 3.6/4.0

BE(Bachelor of Engineering), Electronics and Communication Engineering (Aug 2001 - May 2005)

Visveswaraiah Technological University. Karnataka, India.

EXPERIENCE & SKILLS

Two years of considerable Cleanroom Environment (Class 1000 cleanroom facility) Experience with semiconductor fabrication processes like oxidation, diffusion, photolithography, etching and metal deposition. (Jan 2008- Dec 2009)

MS (Thesis): Graduate Research Assistant (GRA) at The University of Texas at Arlington

Pyramidal microstructure of ZnO (Zinc Oxide) as an Antireflective coating for Solar Cell (Sep 2008-Dec 2009)

• Deposition of PECVD Silicon nitride as hard mask and annealing.

• Thin film deposition (Silicon nitride, Silicon dioxide, ITO) using PVD and PECVD.

• Optimizing the photolithography and etching time of the Silicon nitride film.

• Optimizing the wet etching time of silicon to make Inverted Pyramid.

• Optimizing time, temperature and thickness the deposition of Zinc Oxide using electrochemical method.

• Optimizing the deposition time and thickness of ITO using sputtering.

• Wet etching experiments to optimize etching time of thin films such as Silicon dioxide, Silicon nitride.

• Characterization using Reflectometer, Ellipsometer, SEM and XRD.

• Electronic band-gap calculation of ITO and Zinc Oxide film using Spectrophotometer.

• Tools Used : AJA Sputter System, PECVD(Trion Orion II), Potentiostat(Electrochemical Deposition), Convective Assembly Thin Film deposition, Profilometer(KLA-Tencor Alpha-Step IQ Profilometer), Reflectometer(Ocean Optics NC-UV-VIS Reflectometer), SEM(Hitachi S-3000N Variable Pressure SEM), EDS, XRD, Spectrophotometer(JASCO V-570 UV/VIS/NIR.)

Characterization and Wire Bonding Experience: Mobility extraction of High-k Dielectric (Jan 2008- May 2008)

• Characterization of MOSFETs and Hall Bar using C-V and I-V analysis to determine the inverted channel charge, Mobility.

• High Frequency analysis of MOSCAP to determine different electrical parameters.

• Wire bonding of devices using gold wire to aluminium contacts.

• Tools Used: Electrical Test Station (Agilent 4155C and 4284A) and Kulicke & Soffa Model 4524 Ball Bonder.

Graduate Teaching Assistantship Experience (GTA)

Silicon IC Fabrication Laboratory (Sep 2008-May 2009)

• Assist graduate students in understanding the operation and theory of the experiments such as thermal oxidation, diffusion, photolithography (MJB3 Karl Suss Mask Aligner) and metal deposition and wet etching.

• MOS Capacitors and p-n junction were fabricated and characterized.

• Tools Used: Oxidation Furnace, Diffusion Furnace, MJB3 Karl Suss Mask Aligner, Thermal Evaporator(NRC Thermal Evaporator), Thermal Evaporator(NRC Thermal Evaporator), Micromanipulator 8060-US8-V0-1-A Electrical Test Station(Agilent 4155C and 4284A).

Undergraduate digital circuit laboratory (Jan 2008- May 2008)

• Assist undergraduate students with the implementation of circuit and manage the inventory work.

Experience and Skill with Cleanroom Tools

• Characterization tools: Micromanipulator 8060-US8-V0-1-A Electrical Test Station(Agilent 4155C and 4284A), Profilometer (KLA-Tencor Alpha-Step IQ Profilometer), Veeco FPP-5000 Four-point Probe, Gaertner Ellipsometer, Reflectometer (Ocean Optics NC-UV-VIS Reflectometer), SEM(Hitachi S-3000N Variable Pressure SEM), EDS, XRD, Lifetime tester(SUNS-VOC-150 Sinton Consulting INC.), Spectrophotometer(JASCO V-570 UV/VIS/NIR), Newport Solar Simulator Am1.5.

• Deposition Tools: AJA Sputter System, PECVD (Trion Orion II), Thermal Evaporator (NRC Thermal Evaporator), Potentiostat (Electrochemical Deposition), AJA E-Beam Evaporator, Thin Film Deposition (ITO, Zinc Oxide thin Film, and silicon nitride), Convective Assembly Thin Film deposition.

• Etching tool: DRIE (TRION Deep Reactive Ion Etching).

• Photolithography: MJB3 Karl Suss Mask Aligner.

SOFTWARE SKILLS: MATLAB, Cadence, PSPICE, C++, Windows OS, MS Office.

RESEARCH PAPERS AND PROJECTS

Silicon IC Fabrication Technology

• Parameter extraction for Deal-Grove oxidation model

• Determination of diffusion coefficients for phosphorus

• Determination of thickness of photoresist layer as a function of spin speed.

• Fabrication and characterization of a MOS capacitor and p-n junction and C-V analysis of MOS-C.

• Metal deposition(Aluminium) and wet etching of silicon dioxide and metal such as Aluminium.

Introduction to MEMS

• Surface Micro machined Metallic Needles.

Digital VLSI Design:

• Design of XOR using CMOS complex logic(Fall2008):It dealt with the design of simple XOR gate with the use of CMOS complex gate and to drive a load of 50 ohm and a capacitor of 150fF

• Design of D-Latch using CMOS Complex logic (Fall2008): The D-latch was designed using NAND CMOS Complex logic and the load was of 50ohm and 100fF.

COURSES TAKEN

Solar cell Material and Devices, Introduction to MEMS, Semiconductor Device Theory, Electronic Materials: Principles and Applications, Digital VLSI Design I.

References: Available upon request.

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