Design Electrical

Nandakumar Vasudevan

**** ******* ******, *** **** , CA-95136 Email : ***********@*****.*** Phone : 408-***-****

Objective

Seeking a challenging full time position as an ASIC designer that stimulates constant learning and provides sustained growth opportunities.

Summary

• 8 yrs experience in RTL coding, verification, Synthesis, Physical Design Support and post silicon bring up.

• In depth knowledge of video processing concepts, NTSC/PAL stds, scaling, interlacing, TV fundamentals.

• Proficient in Verilog and skilled in using Synopsys Design Vision, Primetime.

• Competent in Logic Design, Static Timing Analysis and strong grasp of ASIC design Flow.

• Held direct reports and mentored junior engineers both local and abroad. Experienced in leading projects, quick learner of new design ideas and always up for facing new challenges.

Education

University of Michigan, Ann Arbor Sep 02 – Dec 04

Master of Science in Electrical Engineering and Computer Science. GPA – 3.5/4.0

University of Madras, India Sep 98 – July 02

Bachelor of Engineering in Electrical and Electronics Engineering. GPA – 3.8/4.0

EDA TOOL Experience

Synopsys : Design Compiler/Design Vision, Primetime, Powertheater, Simvision.

Cadence : Ambit, Ncsim, AMS, RTL Compiler, Conformal, ICFB.

Mentor Graphics : Modelsim, ADMS, ICstation, Design Architect.

Experience

Maxim Integrated Products – Senior Member of Technical Staff Oct 11 – Present

Ambient Light / proximity / RGB Sensor Controller and Sequencer specification and development

Methodology Improvements for reducing Top Level Simulation time using System verilog.

Maxim Integrated Products - Member of Technical Staff Aug 08 – Sep 11

Quad NTSC/PAL Video Decoder with audio Codec and Frame Sync

Implemented the programmable Scaler Block in ITU656 standard with Timing Reference Signals of this ~1.4 million gates chip. Modified the FIFO architecture and used clock gating for achieving low power.

Designed horizontal, vertical LPFs, poly phase filters and a 20 bit Wallace tree multiplier using carry save addition and booth encoding to perform the arithmetic in one 27MHz clock cycle.

Designed the output formatting block for various modes of operation including pixel multiplexing and frame multiplexing and CGM block for generating various synchronized versions of the clocks.

Assisted with FPGA emulation (scaler block) and supported DDR2 controller integration.

Instrumental in developing a verification plan for the entire chip and created Verilog AMS models for analog. Assisted with checkers and monitors development. Supported mixed signal simulation.

Developed synthesis scripts for modules in T18 process & worked with ATPG team for scan vector generation. Assisted the physical design team with clock trees and congestion relates issues.

Worked closely with the testing team for developing a test methodology for running at speed tests.

LCD Display Driver Product Lines with 8/16 ch Programmable Gamma , VCOM and MTP

• Responsible for owning the digital potion of the chip and taking it from micro architecture specification through all the facets of ASIC design till tape out.

• Designed the Multiple time programmable (MTP) memory controller and I2C serial interface.

• Implemented the FSM to control the MTP program sequence and read sequence. Verified using logic simulators. Implemented self checking test benches. Synthesized the design and optimized for area.

• Interfaced with back end engineers to support Physical Design. Performed STA and gate level sims.

• Performed LEC and supported post silicon bring up, characterization and GBD analysis.

Video decoder IP

Responsible for verification of Video decoder IP that converts NTSC,PAL into digital component video.

Developed test cases to test each and every sub module of the decoder including the 2D comb filter.

Modified and added extra on chip memory to compensate for field length error.

Responsible for inserting MBIST wrappers and SCAN chains and other port muxing functions.

Developed synthesis scripts to assist with Synthesis and place and route.

Hybrid Die

Spearheaded the integration of two dies in different processes to form a hybrid die.

Led the definition of the interface between the two dies and redefined the testing strategy.

Explored the idea of integrating more than one serial interface to attract a wider variety of customers.

Responsible for leading the digital portion of the chip with a team of two digital designers.

High Speed Current Sense Amplifiers with 12 bit ADC’s Product Lines

• Implemented the FSM for automatic gain control of the ADC control loop

• Designed the address pin of the I2C interface such that the part has multiple addresses

• Instrumental in defining the architecture of the interface between the ADC, current sense amplifier and the digital block.

• Responsible for taking the product from definition to RTL design to verification, synthesis, place & route and tape out and post silicon bring up.

Maxim Integrated Products - Associate Member of Technical Staff Mar 05 – Jul 08

OLED Column Driver with Auto cal

• Assisted with micro architecture specification and supported Synthesis for the entire chip

• Compared synthesis results with Ambit and Design compiler to evaluate design trade offs

• Supported Top level verification and customized the P&R flow to suit each column.

Attended training sessions for Synopsys Advanced Synthesis and Matlab Filter Design Techniques

Interface Design for set top boxes, current sense amplifiers, Class D audio sub system

• Designed and implemented interfaces and digital blocks for various sub systems.

• Held traning sessions for analog designers for the use of logic simulators.

CourseWork

VLSI Design I & II, Electronic Circuits, Digital Integrated Circuits, Logic Ckt Optimization & Synthesis, Microprocessor and its applications, CAD Verification of Digital Systems, Microelectronic Process Technology

Projects Design of a Chess Processor (TSMC 0.18µm CMOS 6M process - EECS 627) May 2003

• Responsible for designing the move generator in the Chess processor (containing 750,000 transistors).

• Novel architecture for the move generator using the solution to the 8 queen’s problem.

• Completed the design flow including architecture design, synthesis, local/global routing, floor planning and verification. SDF back annotated and timing closed. Clock frequency - 100 MHz.

Solid State Device Laboratory - Clean Room Experience Dec 2003

• Fabricated NMOS transistors, diodes, oscillators in a 4inch silicon wafer. Minimum feature size 1 µm.

• Performed oxidation, diffusion, etching, photolithography and DC characterization.

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