Design System

ATIF KHAN

uo0ffb@r.postjobfree.com **** W **th Street Apt 7, Los Angeles, CA 90007 323-***-****

Objective: To get a full-time position in VLSI Industry where I can use my analytical and technical skills for the growth and

Development of organization

EDUCATION

MASTER OF SCIENCE, ELECTRICAL ENGINEERING Aug 2008- May 2010

UNIVERSITY OF SOUTHERN CALIFORNIA [GPA: 3.5]

Coursework: Digital System Design Tool and Techniques, Computer System Architecture, Diagnosis and Design of Reliable Digital Computers, VLSI SYSTEM DESIGN A/B, CMOS VLSI DESIGN, Computer System Organization, Introduction to Programming(C++)

BACHELOR OF SCIENCE, ELECTRONICS AND COMMUNICATION ENGINEERING Aug 2004-May 2008

RTMNU (Nagpur, India)

Coursework: Digital Signal Processing, Microprocessor (8085,8086), Linear Electronic Circuits, Electronic System Design, Digital Communication, Mobile Communication, UHF & Microwave, Computer Communication and network, Electronics Devices and circuits, Electromagnetic Field, C and Data Structure

WORK EXPERIENCE

Directed Research (USC) Jan 2010 –May 2010

Worked on the enhancement of Tomasulo processor by adding Free Register List, Copy Free Check pointing, Return Address Stack.

Walking backward and forward in case of mis-prediction was also carried out. The improved processer will be used as a Course Project in Digital System Design Course

TECHNICAL SKILLS

Languages: Verilog, VHDL, SystemVerilog, C, C++, Perl, TCL Script, UCF, MATLAB, Assembly Language (8085/8086)

Design Tools: Cadence Virtuoso, Xilinx ISE Web pack, ModelSim , Altera Quartus 2, ePD, HSPICE, Nanosim, Simple-Scalar, Real Estimator, Cacti, OrCAD, MultiSim, SPEC Benchmark , NCSim , Digilent Adept , Cosmoscope , Synopsys Design Compiler

Technical Skills: Digital Design, FPGA, ASIC, DFT, BIST, CMOS, Layout Design, Static Timing Analysis, DRC, LVS

Operating System: Win7/Vista/XP, UNIX

PROJECTS:

DDR2 SDRAM Memory Controller Design (Verilog): Controller to carry out Scalar, Atomic and Block Read/Write with Denali DDR2 Model using NC-Verilog. The controller has a simple FIFO based front end Architecture. The code was synthesized using Synopsis

Design Compiler with the help of TCL script.

Test Generation for an FPGA Chip (C++): Led a team of 5 to develop a test generation system consisting of Preprocessor, an ATPG and a Fault Simulator. Designed a preprocessor whose task was creating a reduced fault list Using Fault Equivalence and Dominance and design of Good Circuit Simulator with Inertial, Rise and Fall Delay

Out of Order Processor using Tomasulo Algorithm (VHDL): Out of Order processor which used Register renaming to remove Date Hazards. Designed various units like Instruction Fetch Unit, Dispatch Unit, Issue Unit, Reorder Buffer, Branch Prediction Buffer. Synthesis was done using Xillinx ISE. The code was tested on Spartan-3E FPGA

Student Database System (C++): A student database with ability to do add, delete, sort entries was done. Binary search was done to find elements. Both Linked List and STL based implementation was done to add, delete entries

16 bit Motion Estimator for DSP (Cadence Virtuoso): ME kernel was designed which contained two 2.048 kb SRAM, 24 bit Ladner Fischer Adder and an accumulator. DRC and LVS was carried out on the layout. Stimulus file was written and result was verified on Nanosim. Logical Efforts were used to reduce the delay in circuit.

Neural Network chip Design (Cadence Virtuoso): Designed a neuron that emulated a football Quarterback. Efforts were made to reduce Area-Delay Product

Performance Boosting of CPU (Simple Scalar, Real Estimator, Cacti): Reconfigured parameter of baseline processor to get higher MIPS rating

Single Cycle, Multi Cycle, Pipelined CPU (ePD): Schematic level design was implemented.

Other HDL projects: Lux Meter, I2C, Keyboard Controller with Debounce, Pipelined CPU

Extracurricular Activities/Achievements

• Graded as superior student in Computer System Organization and Digital System Design Course

• Won 2nd prize in VHDL coding completion in Kriti’08 at Raisoni College of Engineering, Nagpur India.

• Executive member of Communiqué a student’s body during 3rd year of College

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