digital design engineer

FRANCOIS THEODOROU

**** ****** ***** **** #***

AUSTIN, TX 78735

EMAIL: ******@*****.***

SUMMARY

Over 14 years of experience designing modules for wireless chips.

Strengths include schematics, layouts and simulations of high-speed low-power digital modules, using different design tools.

PROFESSIONAL EXPERIENCE

Design engineer at Texas Instruments France, 1991 - 2005.

Design engineer at Texas Instruments Austin, 2006 - 2009.

• 2007-2009: In charge of 3 sub-blocks of Modena low power core module for OMAP 4, using internal data path and Magma tools: cells placement (data path structure) done with TI internal tool (EVE/SDP), routing and critical paths analysis done with Magma Talus, RTL vs. layout verification done with Verplex LEC.

Responsible also of Modena top level RTL vs. layout verification, using LEC.

• 2005-2006: Designed Scoreboard custom block which is part of the Ferrari low power core module used in OMAP 3430. This implies creating transistor level schematics and cell layouts (with Cadence Virtuoso), SPICE simulations, manual cells placement and module routing, performance analysis (timing, area and power).

• 2004: Responsible of the multiplier custom block used in the Ryujin CPU. This includes creating transistor level schematics and cell layouts (with Cadence Virtuoso), SPICE simulations, block creation by cells placement and routing, performance analysis. Work performed in Tsukuba, Japan.

• 2002-2003: Synthesized, with the LEAD3 CPU team, the CPU core, using a new process to achieve speed enhancement.

Led serial port module design, wrote the design specification, coded RTL, ran verification simulations written by the verification team and performed synthesis.

Work on OMAP 1610 modules assembly.

• 2000-2001: Designed hardware accelerator dedicated to computing the Viterbi algorithm. Led writing of the C model, assembly test cases and VHDL model and performed functional verification and synthesis (with Synopsys tools).

• 1997-2000: Led the development of the Dual Multiplier Accumulator (DMAC) module for LEAD3 CPU. Responsible for the functional and design specifications, design, VHDL development, functional verification and synthesis.

Technically led the LEAD3 CPU Data Unit.

• 1995-1997: Modified the port interface, timer, serial port, wait and analysis modules using Mentor Graphics’ GDT tools. Work performed in Tokyo, Japan.

Implemented feedback logic needed for cLEAD CPU at-speed test purposes. Work performed in Tokyo.

Led writing of a test specification, for a DSP core, based on PSA (parallel signature analysis)/scan approach and development of test cases to check the functionality of the feedback logic.

Managed sub-contractor team in charge of re-writing the cLEAD test cases. Work done in Houston, Texas.

• 1994: Designed emulation and test port modules using Mentor Graphics’ M language, performed schematic and layout simulations.

• 1993: Responsible of data base management as well as generation and checking of top level layout pattern generation data.

Also in charge of writing script used for ROM programming.

• 1992: Performed digital library cells design and characterization. In charge of library maintenance.

• 1991: Digital filters design, use of Mentor Graphics tools: M model, GDT, LSIM, Genie language. Worked on module design using M model (June – August in Houston, Texas) and on digital filters synthesis with Mentor Graphics tools (August – September in Dallas, Texas).

EDUCATION

1987: Masters in Electrical Engineering at Ecole Centrale de Lyon, France.

1987-1990: Doctoral course work in Micro-Electronics at Ecole Centrale de Lyon, France.

EDA TOOLS AND SOFTWARE LANGUAGES

Cadence Virtuoso, Magma Talus, Design Compiler, GDT schematic and layout, Verilog, VHDL, SPICE, HSIM, Calibre, ModelSim, Pathmill, PrimeTime, Verplex LEC, C, Unix csh/tcsh, perl, awk, sed, Tcl, Clearcase.

PERSONAL

French citizenship with green card.

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