Engineer Engineering

Charles F. Musante

** ****** ***** ****: 802-***-****

South Burlington, VT Email: ***.****@*****.***

Objective

Obtain a challenging semiconductor engineering position in an organization where an experienced, dedicated, highly motivated individual with a proven track record of accomplishments is needed.

Summary of Technical Experience

Over 29 years of experience in semiconductor engineering

Process Engineering/Integration: Manufacturing and research experience in most of the major areas associated with semiconductor engineering. Diffusion, thermal oxidation, wet etching, plasma etching, PECVD/HDP-CVD, LPCVD and ALD of silicon-based and tungsten thin films, metallization, and photolithography. Through Silicon Via (TSV) integration experience along with thin TSV wafer finish integration experience.

CMOS BEOL Process Integration: Extensive experience in BEOL process integration for CMOS circuits/devices, including Low-K dielectrics and HiK MIM development. Additional matrix responsibilities for BEOL plasma charge damage.

Device Fabrication: Broad experience in fabrication of discrete devices and VLSI/ULSI circuits, including: MOSFETs, BJTs, HEMTs, CMOS Image sensors, semiconductor lasers and superconducting frequency mixers. Technology families include CMOS/BiCMOS/SiGe utilizing both aluminum and copper BEOL metallization.

Functional Test/Characterization: Five years of experience working on CMOS image sensor pixel design development, focused on test/characterization of IBM designed pixel arrays. Additional duties in experimental design, process integration and pixel design.

Technical Documentation: Adept at developing technical documentation and project management.

Problem Solving: Over twenty nine years of experience in the semiconductor field, most of it spent solving technical problems across a broad spectrum of materials, processes and devices.

Employment History

IBM Corporation - Essex Junction, VT January 2001 to Present

Technology Development Engineer (current position)

Technical leader for advanced SOS integration program

o Responsible for developing a manufacturable process for CMOS Silicon on Sapphire

o Process development/integration, equipment procurement, reliability qualification

Program manager for TSV wafer finishing at IBM / Burlington

o Responsible for all aspects of enabling wafer finishing for tungsten TSV wafers.

o Program management, budget, resources, equipment selection and procurement, process/reliability qualification, technical development

CMOS Image Sensor Test/Characterization Engineer

Responsible for all things related to test, test development and functional characterization of image sensor arrays

Developed novel test protocols for critical image sensor metrics, including Shutter Rejection Ratio, Photo-Response linearity and multiple device leakage measurements

Manufacturing Process Engineer, Novellus Dielectric and Tungsten Deposition, Jusung HiK CVD

Manufacturing engineering support for 26 CVD mainframes in a high volume, complex Fab

Processes supported include Chemical Vapor Deposition (CVD) of tungsten interconnect films and Plasma Enhanced Chemical Vapor Deposition (PECVD, HDP-CVD) of dielectric films.

Low-k process integration for Cu BEOL technology

Broad responsibilities in the areas of yield enhancement, OEE improvement and manufacturing engineering leadership

Matrix responsibilities included HiK MIM development (tool, process), BEOL plasma charge damage mitigation across all bulk technologies, Color Imager Yield Team and 90nm technology transfer.

University of Massachusetts. – Amherst, MA January 1990 to December 2000

Research Engineer, Department of Electrical and Computer Engineering

Developed device fabrication procedures for a variety of semiconductor device research projects, including III-V transistors, optoelectronic devices and superconducting frequency mixers.

Supported all fabrication and test equipment related to department’s semiconductor research and instructional effort.

Managed all aspects of a Class 10,000 cleanroom facility, and managed the day-to-day activities in two III-V epitaxial growth laboratories.

Served as the laboratory instructor for department’s microfabrication course (ECE 571).

Authored the laboratory manual and associated documentation for ECE 571.

Designed and implemented a state-of-the art epitaxial growth laboratory, the centerpiece of which was an Aixtron 200/4 epitaxial growth system.

Served as Departmental Safety Coordinator and worked with Environmental Health and Safety officials to establish safety protocols for semiconductor research and instructional laboratories.

University of Massachusetts. – Amherst, MA May 1985 to December 1989

Professional Technician, Department of Electrical and Computer Engineering

Designed and implemented a Class 10,000 cleanroom facility for microelectronic fabrication.

Developed a process for fabricating microelectronic test structures utilizing the NBS-4 Mask Set.

Developed silicon micro-machining processes for use in departmental research.

Installed and supported major new process tools: Reactive Ion Etcher, Plasma Deposition System, Metal PVD System, Electron-Beam Metal Evaporation System, and a Scanning Electron Microscope.

Digital Equipment Corp. – Hudson, MA April 1984 to May 1985

Technician III, Advanced Manufacturing Engineering

Provided manufacturing process support for thin films in conjunction with DEC’s NMOS and MicroVAX products. Systems supported included: diffusion, oxidation, LPCVD of oxides, nitrides and polysilicon, and metal deposition.

Project work included a successful investigation into the source of metal-one to metal-two short circuits.

Education

University of Massachusetts -- Amherst, MA 1990

Bachelor of Science in Solid State Engineering

• Graduated cum laude

Patents

• 14 filed patents

Publications

Multiple IBM publications (some are listed below)

A.J. Gatesman, J. Waldman, M. Ji, C. Musante and S. Yngvesson, “An Anti Reflection Coating for Silicon Optics at Terahertz Frequencies”, IEEE Microwave and Guided Wave Letters, vol. 10, pp.264-266, July 2000.

E. Gerecht, C.F. Musante, Y. Zhuang, K.S. Yngvesson, T. Goyette, J.C. Dickinson, J. Waldman, P.A Yagoubov, G.N. Gol’tsman, B.M. Voronov and E.M. Gershenzon, “NbN Hot Electron Bolometric Mixers-A New Technology for Low-Noise THz Receivers”, IEEE Transactions on Microwave Theory and Techniques, vol. 47, pp.2519-2527, Dec. 1999.

E. Gerecht, C.F. Musante, H. Jian, K.S. Yngvesson, J. C. Dickinson, J. Waldman, P.A Yagoubov, G.N. Gol’tsman, B.M. Voronov and E.M. Gershenzon, “New results for NbN Phonon-Cooled Hot Electron Bolometric Mixers Above 1 THz”, IEEE Trans. Appl. Superconduct., vol. 9, pp. 4217-4220, June 1999.

E. Gerecht, C.F. Musante, K.S. Yngvesson, J. Waldman, G.N. Gol’tsman, P.A. Yagoubov, B.M. Voronov and E.M. Gershenzon, “Optical Coupling and Conversion Gain for NbN HEB Mixer at THz Frequencies”, Intern.Semicond.Device.Res.Symp., Charlottesville, VA. Dec.1997.

E. Gerecht, C.F. Musante, C.R. Lutz, Jr., Z. Wang, J. Bergendahl, K.S. Yngvesson, E.R. Mueller, J. Waldmen, G.N. Gol’tsman, B.M. Voronov, E.M. Gershenzon, “Hot Electron Mixing in NbN at 119 Micrometer Wavelength”, Proc. Intern. Semicond. Device Res. Symp., Charlottesville, VA, Dec. 1995, p.619

J.X. Yang, J. Li, C.F. Musante and K.S. Yngvesson, “Microwave Mixing and Noise in the Two-Dimensional Electron Gas Medium at Low Temperatures”, Appl. Phys. Lett. 66 (15), 10 April 1995.

B.N. Gomatam, N.G. Anderson, F. Agahi, C.F. Musante and K.M. Lau, “Comparison of Tensile-Strained and Lattice-Matched GaAs(P)/AlGaAs Quantum-Well Reflection Modulators”, IEEE Photonics Technology Letters, May, 1993

J.X. Yang, F. Agahi, D. Dai, C.F. Musante, W. Grammer, K.M. Lau and K.S. Yngvesson, “Wide-Bandwidth Electron Bolometric Mixers: A 2DEG Prototype and Potential for Low-Noise THz Receivers”, IEEE Transactions on Microwave Theory and Techniques, Vol. 41, No.

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