Project Design

CURRICULUM VITAE

Akhil Sankati E-Mail: ************@*****.***

M.Tech, Electronic Instrumentation Mobile: +91-973*******

SYNOPSIS:

• Six months experience in Power Processor Verification.

• Good understanding of digital design concepts and processor architectures.

• Good exposure of unit level functional formal verification.

• Good programming skills in VHDL and Verilog HDL.

• Had done FPGA related mini project in academic course.

OBJECTIVE:

Seeking a position in the organization that gives me an opportunity to show my skills and improve my knowledge in the VLSI.

EDUCATIONAL QUALIFICATION:

Course Board/Education Name of the Institution Year of Passing Percentage/CGPA

M.Tech NIT, Warangal NIT, Warangal 2010-2012 7.6(till 3rdSem)

B.Tech KU, Warangal KITS, Warangal 2005-2009 74.13

12th Board of Intermediate Education, AP Sri Vijetha Junior College, Warangal 2002-2004 92.4

S.S.C Board ofSecondary Education,AP Sri GurukulaVidyalayam, Narsampet 2001-2002 79.17

TECHNICAL SKILLS:

Languages: VHDL, Verilog HDL and C.

Verification Skills: Unit level functional formal verification

Operating System: Windows XP/7, LINUX and AIX.

Tools: Xilinx ISE, Quartus, Labview, MATLAB and IBM internal Tools (SixthSense).

RELATED SUBJECTS:

# Digital system design # VLSI Technology

# PC Based Instrumentation # Display and Data Acquisition System

CURRICULUM PROJECTS:

M.Tech (Main Project) (Internship):

Organization : IBM Systems and Technology Group, Processor Development

Duration : 6 Months (Jan, 2012 to June, 2012)

Project Title : Formal Verification of Floating Point Divide Logic using Sixth Sense Tool

Description:

FPU is one of the execution units of processor core which is responsible for all floating point operations. FPU supports simultaneous multi threading (SMT) execution mode. Corner-case bugs of such unit are artifacts of simulation since they are not detected due to the non-exhaustive nature. Formal verification is the best methodology for such designs since it algorithmically and exhaustively explores all possible input values overtime. Formal verification is the attempt to prove the correctness of a design for all data and all scenarios against the properties (specifications). FV includes Model Checking, Combinational Equivalent Checking and Sequential Equivalent Checking. The coverage will be increased.

Team Members: 3

Responsibilities:

• Developing the reference model for the Divide instruction of FPU.

• Developing driver and monitor for FPU.

• Debugging the bugs.

• Automate the formal verification environment.

M.Tech (Mini projects):

TITLE: FPGA Implementation of RS 232 to GPIB Converter in VHDL.

Description: To develop a RS 232 protocol on the FPGA that enable to connect it to PC and an instrument using GPIB Protocol interface.

This can be achieved by

1. Interfacing the PC and controller (FPGA) using RS-232 protocol

2. Interfacing controller and instrument using GPIB protocol

TITLE: Design and Implementation of 32 bit ALU(division and multiplication) in VHDL.

Description: Implementation of ALU architecture was done in vhdl. Basic Arithmetic

and logical operations were implemented.

Main Project (B. Tech)

TITLE: Design and Implementation of CMOS Bandgap Reference without Resistors

Description:

This project describes a bandgap reference designed in a 0.6µm digital CMOS technology without resistors. The circuit uses ratioed transistors biased in strong inversion together with the inverse function technology to produce a temperature-in-sensitive gain applied to the propositional to absolute temperature (PTAT) term in the reference. After trimming, the peak to peak output voltage is insensitive to temperature. It occupies less space, low power dissipation and requires less power supply.

The design of this bandgap reference is implemented using virtuso schematic tool and analog design environment of Cadence tool.

ACHIEVEMENTS:

• I Stood College 1st rank in my Intermediate level.

• Secured 97.84% in GATE.

PERSONAL DETAILS:

Permanent Address:

H.No. 1-59,

Kammapalli (Village),

Narsampet (Mandal),

Warangal (Dist),

Andhra Pradesh,

506331

Languages Known: English & Telugu.

I hereby declare that all the above information furnished is true and correct.

Place: Signature

Date: Name: AKHIL SANKATI

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