QUAN BAI

**** ******** ***, ******, ** *****

925-***-**** (cell); u9dtw0@r.postjobfree.com

SUMMARY

Senior process engineer with expertise in thin-film and substrate properties and processing, six-sigma methodology, and failure analysis by modern analytical techniques. Work experiences in plating, thermal spray coating, dice, polish, chemical stripping, precision cleaning, soldering, flip chip die attach, and liquid crystal panel processing, for disk drive, fiber optics, liquid crystal display, semiconductor process tool and MEMS industries. Extensive records in control, improvement and development of industrial processes in mass- and low-volume production environments. A trustworthy, hard working and productive team player with strong educational background in materials science and multi-national work experiences.

PROFESSIONAL EXPERIENCE

FormFactor Inc, Livermore, CA 2007 To Present

Sr. Principle Process Engineer

Responsible for process engineering of chip joining process in MEMS probe card manufacturing, involving flip chip die attach, soldering and probe xyz position error metrology.

Provided sustaining and CIP engineering support for die attach manufacturing using CDB50 Flip Chip Bonder with 2um accuracy, as well as VIEW optical measuring system metrology. Completed various CIP projects including corner die treatment, special epoxy patterning, new laser inspection algorithm and quantitative tip-attach error measurement, which substantially reduced die assembly failures and cycle times.

Optimized and qualified new soldering process using ATV reflow oven for tip attach of probe cards through DOE. Transferred the soldering processes to production through training, documentation and SPC implementation.

Carried out R&D of joining processes for new probe cards, involving precision die joining by die placement, epoxy and soldering.

Completed a 3-month oversea assignment for the build of a new manufacturing facility in Singapore.

Tosoh SET Inc, Dublin, CA 2003 To 2007

Sr. Process Engineer

Responsibilities encompass process engineering, failure analysis, R&D and technical interface with subcontract vendors for semiconductor process tool manufacturing and refurbishing, that involve metal/ceramic surface texturing, thermal spray coating (twin-wire arc spray and plasma spray), deposition removal by chemical & mechanical stripping, precision cleaning, and surface property and cleanliness characterizations through coating adhesion, surface particle, ionic contamination, microscopy and out-gassing analyses.

Developed a novel plasma spray ceramic coating for quartz bell jars used in etch and pre-clean chambers.

Invented tough thermal spray coatings for PVD chamber components for high-temperature processing environment with improved particle and kit life performances. US Patent is granted.

Implemented patented GPS thermal spray coating for Ti/TiN PVD process kit components.

Completed gauge R&R and DOE studies that identified critical coating process parameters and established their functional relationships with product properties.

Established and maintained SPC system using InfinityQS database for manufacturing.

MicroDisplay Corporation, San Pablo, CA 2002 To 2003

Sr. Process Development Engineer

Responsible for process development and reliability test for transferring prototype LCoS microdisplay products (for near-eye and projection applications) from R&D to production, including class-10 clean-room front-end processes such as rubbing, printing and laminating, as well as back-end processes such as scribe and break, LC-fill and seal, ACF flex attach, die attach and encapsulation.

Developed an effective and convenient method to correct out-of-flat problem in wafers and dies, resulted in excellent cell-gap uniformity and much improved display image quality and reliability.

Invented a unique lamination method using formulated spacers to achieve >98% cell-gap uniformity.

Completed 2 patent disclosures. Given an oral presentation at SID International Conference.

Gemfire Corporation, Fremont, CA 2000 To 2002

Sr. Process Engineer (Plating, Dice & Polish)

Carried out process development, control and problem-solving for electrolytic plating, dice and polish of lithium niobate, glass and polymer wafers for manufacturing of planar waveguides and PhotonIC components for fiber optic telecommunication applications.

Established nickel and gold electrolytic plating lines from scratch. Developed optimum plating processes for manufacturing optical amplifier, VOA and modulator chips. Setup analytical and metrology labs for characterizing plating baths and plated films.

Optimized dicing process for chip singulation from lithium niobate and thick glass-polymer single or composite wafers, resulted in a 5-fold increase of production throughput with improved quality.

Developed angle polish process with high CPK for waveguides, and a chip finish process for glass-polymer composites that avoided polymer cracking while maintained optical finish of chip faces.

Seagate Technology Inc, Anaheim, CA 1996 To 2000

Sr. Process Engineer (Plating and Annealing)

Responsibilities involved process control, improvement and problem solving for electroless nickel plating, cleaning, and stress-relieving processes for magnetic recording substrate manufacturing. Six-Sigma brown belt. Received Seagate Outstanding Employee Award for excellent engineering performances.

Optimized plating bath filtration system, resulted in documented saving of more than $1M per year.

Implemented plating bath bleed-and-feed system that greatly increased production throughput.

Established automated temperature and pH tiering for plating bath, resulted in significant improvement of plating rate/thickness Cpk.

Optimized plating-line hoist auto scheduling, resulted in 25% increase in throughput.

Used automated-ADE thickness sorters to achieve a major process change that switched sorting step from post-plating to pre-plating, resulting in improved process flow and parts identification capability throughout the whole plant production processes.

University of California, Riverside, CA 1994 To 1996

Research Scientist

Performed researches on diffusion and point defect kinetics of solid-state chemical reaction in ceramics. Conducted fund raising and proposal writing to obtain external research grants. Awarded a $100K fund, as a sole principle investigator, from the prestigious US National Science Foundation.

German Federal Research Institute, Berlin, Germany 1993 To 1994

Staff Researcher

Initiated research projects on the effect of hydrogen and partial melting on the electrical and mechanical properties of glass-ceramics.

University of Minnesota, Minneapolis, MN 1990 To 1993

Postdoctoral Research Associate

Carried out research on metal-ceramic/ceramic-ceramic adhesion and hydrogen diffusion using SEM, RBS, FTIR, high-temperature pressure vessel and nano-indentation/scratch test apparatus.

Major research result on hydrogen diffusion in ceramics was published in the prestigious journal NATURE and was commented highly on NATURE’s News & Views column.

Research results on titanium-to-alumina and anorthite-to-mica adhesion were published on major engineering journals and were adopted in the production processes of sponsor companies.

EDUCATION

Cornell University, Ph.D.

Materials Science and Engineering, Ithaca, NY

University of Science and Technology of China, B.S.

Physics, Hefei, China

OTHER TECHNICAL TRAINING/SKILLS

Extensive knowledge of DOE and SPC 6-Sigma methodology and Kepner-Tregoe problem solving and decision-making. Proficient computer skills including Visual Basic, Minitab, JMP, InfinityQS-SPC database, Word, Access, Excel and Project.

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