Design System

D.Likhitha Contact No: +91-872*******

E-mail: ********.**@*****.***

Objective:

To be associated with an organization where my academic and experience can be utilized for the development of the organization as well as improve my inter personnel skills.

Skill Set:

Programming Languages : Verilog, VHDL, C, System Verilog

Functional Simulation : ModelSim (Mentor Graphics), VCS (Synopsys)

Synthesis : Xilinx ISE 10.1 (FPGA), Design Compiler (ASIC)

Physical Design : IC compiler (ASIC), Cadence Virtuoso (Full-Custom)

Static Timing Analysis : Prime-Time

Test Simulation : Tetra Max

Digital CMOS Design : Hspice

Operating Systems : Windows XP, Vista, Linux

Academic Profile:

Degree Institute Year % Marks

M.Sc (Engg) VLSI, MSRSAS, Bangalore 2012 75

B.Tech Regency Institute of Technology,

(AFFILIATED TO PONDICHERRY UNIVERSITY), YANAM 2010 7.6

(CGPA)

IPE Bharathi Junior College, Vijayawada 2006 83

SSC Brilliant Grammar High School, Hyderabad 2004 70

Areas of Interest:

Physical Design

STA/DFT

Verification

RTL Design

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Projects in M.Sc [Engg]:

Main Project:

Title Verification of MIFARE Ultra light for Contactless Smart Card Application at NXP Semiconductors, bangalore

HDLs: Verilog and TCL Scripts

MIFARE Ultra light is used for the Near Field Communication (NFC) and Automatic Fare Collection (AFC) Contactless applications. The design and verification test bench were written in verilog. The Proximity Coupling Device (PCD) to Proximity Card or Object (PICC) and PICC to PCD response are verified using TCL scripts. The complete design along with the scripts is simulated using Cadence NCSim tool.

Title PCB Layout and Analysis for Frequency Counter

Tools Used: Cadence Virtuoso

PCB layout for Frequency Counter by consideration the placement and routing of the critical signals and applying suitable technique. The analysis for crosstalk and reduction techniques, impedance matching and suitable methods to avoid reflection/ringing. Electro-Migration Interface effect is analyzed. Bill Of Material (BOM) for Frequency Counter is obtained and Gerber File are generated for the Frequency Counter.

Title DESIGN AND IMPLEMENTATION OF FIR Filter in ASIC

Tools Used: Xilinx ISE 10.1 Full Suite, Synopsys-Design Compiler, Prime-Time, Tetra-Max, IC Compiler, VCS.

HDLs: Verilog and System Verilog.

FIR Filter is used as a serious of delays, multipliers, and adders to create the FIR Filter. The project deal in the design and implementation of a Lifting Scheme based FIR Filter architecture. The modeling of the design was carried out using Verilog HDL, the implementation process was carried out targeting ASIC. The ASIC implementation was carried out through performing synthesis, static timing analysis, DFT, ATPG, physical implementation by considering 65nm technology libraries, CTS, Power analysis and DRC.

Title Design and Constraint Random Verification for Traffic light controller.

Tools Used: Design Compiler.

HDLs: Verilog HDL, System Verilog

The design verification is done using Design Compiler to check simulation and synthesis results in both Verilog and System verilog. The functional verification of the design was also carried out by direct, random and constraint random stimulus applied to the design by modeling in System Verilog

Title Design and verification of Reconfigurable UART IP core.

Tools Used: Xilinx ISE 10.1, Model Sim.

HDLs: Verilog HDL

UART Verilog RTL code was given to check the simulation and verification process using Xilinx ISE 10.1 and ModelSIM. Based on UART’s working principle asynchronous and synchronous mode of operation was discussed and developed test bench for verification. Simulation and Verification of functionality of the RTL code completed with ModelSIM software. Mealy method finite state machines were used to understand the UART transmitter and receiver functions. Simulated RTL code used in the Xilinx ISE 10.1 tool for generation of hardware of UART code.

Title Microblaze Processor Based Embedded System Design.

Tools Used: Xilinx Platform Studio.

HDLs: Verilog HDL

Microblaze processors are 32-bit RISC soft processer embedded in the Xilinx FGPA for easy customization and obsolescence mitigation. The embedded system supports memory controller, interrupt controller, interrupt handler and software debugger. ChipScope tool was used for debugging an embedded system and for HDL system simulation of processor –based design. Using Virtex-5 FGPA board divider module was interfaced with the Microblaze processor.

Title Analog and Layout Design and Implementation of ALU Design and 6-T SRAM Memory

Tools Used: HSPICE, Cadence Virtuoso Schematic Editor, Layout XL, Spectra, ASSURA

Arithmetic logic unit designed and implemented. This ALU will perform Arithmetic functions like addition, subtraction, increment and decrement, the Logic functions such as AND, OR, IDENTITY, INVERSE and full adder implemented using HSPICE tool. In this design, Manchester carry chain adder was used as full-adder, because it’s very simpler in structure and can be easily modularized in the schematic and layout design. This design is carried out in HSPICE for 180 and 45 nm CMOS technology and checked for varying parameters, and power analysis. The 6T SRAM design had been developed using Cadence Virtuoso Schematic XL editor, Layout XL, Assura, and Spectra. Physical verification with respect to schematic is performed using LVS (layout Vs Schematic) deck. Even 6T SRAM also had done using Cadence Virtuoso.

Title Design of Data Converters and Gilbert Cell Mixer

Tools Used: Cadence Virtuoso.

Data converters are playing vital role in wireless networks. In this assignment schematic of 3-bit successive approximation register(SAR) ADC has been designed and developed along with its sub blocks like DAC, Sample and hold circuit, shift register, comparator and simulated using cadence virtuoso tool and its current, resistor and least significant bits (LSB) had been calculated and output also verified. In another part of this assignment NMOS based Gilbert cell double balanced mixer had been designed. The transistor sizes, width and trans-conductance to develop Gilbert cell double balanced mixer had been calculated and transient analysis and periodic steady state analysis has been carried out to verify the output of mixer through Cadence Spectre RF tool.

Title Designing of Nano-Scale Devices

Tools Used: HSPICE,PSPICE, Nano-hub (online simulation tool)

Nano-scale devices such as Single Electron Transistor, FinFET, Nanotubes, Nanowires, voltages vs. current analysis has been carried out by developing HSPICE code and online simulation tool from Nano-hub website and designing of inverter based on all these Nano-scale devices done. To develop these devices various model files such as predictive technology model, Berkeley’s short channel insulated gate model and compact model files has been discussed with its pros and cons. In another chapter of this assignment, SET based and FinFET based 3-stage and 5-stage ring oscillator to generate different frequencies has been designed and output verified through PSPICE and HSPICE simulation tool.

Papers at postgraduate Level:

“Design and Implementation of 4-bit ALU using FINFETs for Nano Scale Technology” In Proceedings of the International conference on Nanoscience, Engineering and Technology, ISBN: 978–1–4673–0072–8, pp. 231 – 236, November 2011.

“Design and Implementation of 32nm FINFET based 4x4 SRAM cell array using 1-bit 6T SRAM” In Proceedings of the International conference on Nanoscience, Engineering and Technology, ISBN: 978–1–4673–0072–8, pp. 218 – 221, November 2011.

Papers at Undergraduate Level:

Given presentation on the topic “Electronic Nose” at National Level ‘Technical Paper Contest’ at Pragathi College of Engineering.

Profile Summary

6 months of work experience (internship) in ASIC front end verification.

Knowledge on the complete VLSI flow

Hand on experience on verilog, system verilog

Have experience on cadence and Synopsys tools

Knowledge on TCL Scripting

Personal Details:

Name D.Likhitha

Date of Birth 20th August 1989

Gender Female

Marital Status Single

Languages Known English, Hindi and Telugu

Nationality Indian

Contact Address: Alternate Address:

M.S. Ramaiah School of Advanced Studies, D/O D.Srinivasa Rao,

#470-P, Pennya Industrial Area, 4th Phase H.No:16-9-334/2/1,Dhobi Galli,

Bangalore-560054, Old Malakpet, HYDERABAD-500036,

Karnataka. Andhra Pradesh.

I hereby promise that the above details given by me are true and correct to the best of my knowledge and belief.

Place:

Date: D.Likhitha

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